公开(公告)号：US11868643B2

公开(公告)日：2024-01-09

申请号：US17123914

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0653 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0679 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.

公开(公告)号：US11537512B2

公开(公告)日：2022-12-27

申请号：US17507090

申请日：2021-10-21

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

公开(公告)号：US11194709B2

公开(公告)日：2021-12-07

申请号：US16800225

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

公开(公告)号：US11561855B2

公开(公告)日：2023-01-24

申请号：US17530313

申请日：2021-11-18

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/20 ,  G06F12/02

Abstract: A system including a memory device having blocks of memory cells and a processing device operatively coupled to the memory device. The processing device to perform operations comprising: detecting an error event triggered within a source block of the memory cells; reading data from the source block; writing the data into a mitigation block that is different than the source block; and replacing, in a mapping data structure, a first identifier of the source block with a second identifier of the mitigation block.

公开(公告)号：US11249896B2

公开(公告)日：2022-02-15

申请号：US16722717

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Johnny A. Lam ,  John E. Maroney ,  Mark Ish

IPC: G06F12/02 ,  G06F12/0873 ,  G06F9/355 ,  G06F12/0882

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

公开(公告)号：US11216364B2

公开(公告)日：2022-01-04

申请号：US16794016

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Chandra M. Guda ,  Johnny A. Lam

IPC: G06F12/02 ,  G06F12/0864 ,  G06F12/0815 ,  G06F12/0846 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0882

Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.

公开(公告)号：US20210405914A1

公开(公告)日：2021-12-30

申请号：US16912402

申请日：2020-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Johnny A. Lam

IPC: G06F3/06

Abstract: A processing device includes a system tag data structure to store a system tag that includes a logical transfer unit (LTU) identifier corresponding to an LTU, which includes a subset of a plurality of sequential logical block addresses (LBAs) that includes an LBA of a read request, and a mapping data structure that maps a zone of LBA space to physical address space. Hardware logic is to: retrieve the LTU identifier from the system tag; determine a zone identifier (ID) based on the LTU identifier; index, using at least one of the zone ID or the LTU identifier, into the mapping data structure to retrieve metadata that specifies a mapping between the LTU identifier and a physical address of the physical address space; and store the metadata in the system tag data structure in association with the system tag.

公开(公告)号：US20210342267A1

公开(公告)日：2021-11-04

申请号：US17233026

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F12/0804 ,  G06F12/1009

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

公开(公告)号：US10990526B1

公开(公告)日：2021-04-27

申请号：US15929405

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F13/00 ,  G06F12/0804 ,  G06F12/1009

Abstract: A system includes a NVM memory, and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone state and to a zone index; a journal data structure (JDS); and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index, wherein the zone write pointer includes a location in the LBA space; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; update, within the JDS, metadata of the entry of one the ZMDS or the JDS affected by a flush transition between the ZMDS and the HFUT; and in response to an asynchronous power loss event, flush the JDS and the HFUT to a NVM device.

公开(公告)号：US20240078033A1

公开(公告)日：2024-03-07

申请号：US18504898

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.