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    Coherency locking schemes
    2.
    发明授权
    Coherency locking schemes 有权

    公开(公告)号：US11726669B2

    公开(公告)日：2023-08-15

    申请号：US17703818

    申请日：2022-03-24

    申请人： Micron Technology, Inc.

    发明人： Yun Li ,  John Traver

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

    摘要： Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

    Performance control for a memory sub-system
    3.
    发明授权
    Performance control for a memory sub-system 有权

    公开(公告)号：US11520502B2

    公开(公告)日：2022-12-06

    申请号：US16731936

    申请日：2019-12-31

    申请人： Micron Technology, Inc.

    发明人： Yun Li ,  James P. Crowley ,  Jiangang Wu ,  Peng Xu

    IPC分类号： G06F3/06

    摘要： Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

    COHERENCY LOCKING SCHEMES
    4.
    发明申请
    COHERENCY LOCKING SCHEMES 有权

    公开(公告)号：US20220283713A1

    公开(公告)日：2022-09-08

    申请号：US17703818

    申请日：2022-03-24

    申请人： Micron Technology, Inc.

    发明人： Yun Li ,  John Traver

    IPC分类号： G06F3/06

    摘要： Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

    READ COUNTER FOR QUALITY OF SERVICE DESIGN
    6.
    发明申请
    READ COUNTER FOR QUALITY OF SERVICE DESIGN 有权

    公开(公告)号：US20210303340A1

    公开(公告)日：2021-09-30

    申请号：US16828738

    申请日：2020-03-24

    申请人： Micron Technology, Inc.

    发明人： Yun Li ,  Jiangang Wu ,  James P. Crowley

    IPC分类号： G06F9/48 ,  G06F3/06

    摘要： Methods, systems, and devices for a read counter for quality of service design are described. First commands may be assigned to a first queue of a memory die of a memory sub-system, wherein the first queue is associated with a first priority level. The memory die may include a second queue associated with a second priority level different from the first priority level, the second queue comprising one or more second commands assigned. Based at least in part on a counter associated with the first queue and the first and second priority levels, it may be determined that a threshold number of the first commands of the first queue have issued without a command from the one or more second commands having issued. A command from the second commands may issue before issuing a next command of the first commands based at least in part on the counter.

    INTERNAL COMMANDS FOR ACCESS OPERATIONS
    7.
    发明申请
    INTERNAL COMMANDS FOR ACCESS OPERATIONS 有权

    公开(公告)号：US20210278995A1

    公开(公告)日：2021-09-09

    申请号：US16809371

    申请日：2020-03-04

    申请人： Micron Technology, Inc.

    发明人： John Traver ,  Ning Zhao ,  Tom V. Geukens ,  Yun Li

    IPC分类号： G06F3/06 ,  G06F11/07

    摘要： Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.