公开(公告)号：US20230253928A1

公开(公告)日：2023-08-10

申请号：US17583018

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: H03F1/30 ,  H03F3/21 ,  H03F1/02 ,  H02M3/155 ,  G11C11/4074

CPC classification number: H03F1/301 ,  G11C11/4074 ,  H02M3/155 ,  H03F1/0233 ,  H03F3/211 ,  H03F2200/504

Abstract: Systems and devices are provided for tracking bandgap current generated by a bandgap circuit and mitigation of leakage current regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus and comprising a transistor. The apparatus may also include bandgap current mirroring circuitry that generates a mirrored current that mirrors a received current that is process, voltage, and temperature (PVT) independent. The apparatus may also include a bulk voltage generator circuit including an amplifier having an input coupled to the bandgap current mirroring circuitry. Bulk voltage control circuitry is coupled to an output of the amplifier and generates a bulk voltage based on the relationship between the mirrored current and the leakage current.

公开(公告)号：US11632084B2

公开(公告)日：2023-04-18

申请号：US17127172

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Zhi Qi Huang ,  Dong Pan

IPC: H03F3/45 ,  H03F1/30 ,  G11C7/06 ,  H03F1/02

Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

公开(公告)号：US11587602B2

公开(公告)日：2023-02-21

申请号：US17526846

申请日：2021-11-15

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

公开(公告)号：US20220352855A1

公开(公告)日：2022-11-03

申请号：US17243762

申请日：2021-04-29

Applicant: Micron Technology, Inc

Inventor： Wei Lu Chu ,  Dong Pan

IPC: H03F1/30 ,  G05F3/26 ,  H03F3/213 ,  H03F3/45

Abstract: Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

公开(公告)号：US20220343964A1

公开(公告)日：2022-10-27

申请号：US17864237

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G11C11/4074 ,  G11C11/4091 ,  H03H7/06 ,  G11C5/14 ,  G11C7/14 ,  G05F1/575 ,  G11C11/4063

Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.

公开(公告)号：US20220157368A1

公开(公告)日：2022-05-19

申请号：US16950593

申请日：2020-11-17

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G11C11/4091

Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.

公开(公告)号：US20220157365A1

公开(公告)日：2022-05-19

申请号：US16952804

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C11/4076 ,  G11C11/22

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

公开(公告)号：US20220076720A1

公开(公告)日：2022-03-10

申请号：US17526846

申请日：2021-11-15

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

公开(公告)号：US20220068345A1

公开(公告)日：2022-03-03

申请号：US17003163

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G11C11/4074 ,  H03H7/06 ,  G11C11/4091

Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.

公开(公告)号：US11257558B1

公开(公告)日：2022-02-22

申请号：US16988285

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Wei Lu Chu ,  Dong Pan

IPC: G11C29/02 ,  G11C29/12 ,  G11C7/14 ,  G11C29/44 ,  G11C7/12 ,  G11C29/50

Abstract: Methods, systems, and devices for protecting components in memory from overvoltage are described. A memory system may include a voltage regulator coupled with a first voltage source and a reference circuit that is configured to output a reference signal for the voltage regulator. The reference circuit may include a transistor that is used to generate the reference signal. The memory system may also include a protection circuit that is configured to maintain a voltage between a gate of the transistor and a second node of the transistor below an upper voltage limit. The protection circuit may include a comparator that is configured to compare a difference between a voltage of the reference signal output by the reference circuit and a voltage of the first voltage source with a reference voltage. The comparator may control a pull-down circuit coupled with the output of the reference circuit based on the comparison.