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    Integrated Assemblies and Methods of Forming Integrated Assemblies
    51.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210375907A1

    公开(公告)日：2021-12-02

    申请号：US16885720

    申请日：2020-05-28

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: Some embodiments include an integrated assembly having a first deck, a second deck over the first deck, and a third deck over the second deck. The first deck has first conductive levels disposed one atop another. The second deck has second conductive levels disposed one atop another. The third deck has third conductive levels disposed one atop another. A first staircase region extends to the first and second conductive levels, and passes through the third conductive levels. A second staircase region extends to the third conductive levels and not to the first and second conductive levels. Some embodiments include methods of forming integrated assemblies.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    52.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210280597A1

    公开(公告)日：2021-09-09

    申请号：US16811118

    申请日：2020-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

    Abstract: Some embodiments include an integrated assembly having a memory array region which includes channel material pillars extending through a stack of alternating conductive and insulative levels. A second region is adjacent the memory array region. A conductive expanse is within the memory array region and electrically coupled with the channel material of the channel material pillars. A panel extends across the memory array region and the second region. The panel separates one memory block region from another. The panel has a first portion over the conductive expanse, and has a second portion adjacent the first portion. The panel has a bottom surface. A first segment of the bottom surface is adjacent an upper surface of the conductive expanse. A segment of the bottom surface within the second portion is elevationally offset relative to the first segment. Some embodiments include methods of forming integrated assemblies.

    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    54.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20210126009A1

    公开(公告)日：2021-04-29

    申请号：US16667704

    申请日：2019-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Xuan Li ,  Adeline Yii

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

    Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

    METHODS OF FORMING MICROELECTRONIC DEVICES
    55.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES 有权

    公开(公告)号：US20250017007A1

    公开(公告)日：2025-01-09

    申请号：US18347752

    申请日：2023-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

    IPC: H10B43/27 ,  H01L21/768 ,  H10B43/10 ,  H10B43/35

    Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

    Microelectronic devices including corrosion containment features, and related electronic systems and methods
    56.
    发明授权
    Microelectronic devices including corrosion containment features, and related electronic systems and methods 有权

    公开(公告)号：US12127400B2

    公开(公告)日：2024-10-22

    申请号：US17648708

    申请日：2022-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary

    IPC: H10B43/27 ,  H01L21/768 ,  H01L23/532 ,  H10B41/27

    CPC classification number: H10B41/27 ,  H01L21/768 ,  H01L23/53271 ,  H10B43/27

    Abstract: A microelectronic device comprising a stack structure comprising a non-staircase region, a staircase region, and an array region. Each of the non-staircase region, the staircase region, and the array region comprises tiers of alternating conductive materials and dielectric materials. One or more pillars are in the non-staircase region and in the array region, and one or more supports are in the staircase region. A conductive material is in each of the non-staircase region, the staircase region, and the array region and extends vertically into a source adjacent to the tiers. The source comprises corrosion containment features in each of the non-staircase region, the staircase region, and the array region, adjacent to the conductive material in the source. Additional microelectronic devices, electronic systems, and methods are also disclosed.

    Microelectronic devices, memory devices, and electronic systems
    58.
    发明授权
    Microelectronic devices, memory devices, and electronic systems 有权

    公开(公告)号：US11917817B2

    公开(公告)日：2024-02-27

    申请号：US17125200

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

    IPC: H10B43/50 ,  H10B41/27 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

    Integrated assemblies and methods of forming integrated assemblies
    60.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US11889691B2

    公开(公告)日：2024-01-30

    申请号：US17211580

    申请日：2021-03-24

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

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