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公开(公告)号：US11889691B2
公开(公告)日：2024-01-30
申请号：US17211580
申请日：2021-03-24
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , Dong Wang , Rui Zhang , Da Xing , Xiao Li , Pei Qiong Cheung , Xiao Zeng
Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
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公开(公告)号：US20250151276A1
公开(公告)日：2025-05-08
申请号：US19018899
申请日：2025-01-13
Applicant: Micron Technology, Inc.
Inventor： Pei Qiong Cheung , Zhixin Xu , Yuan Fang
Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
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公开(公告)号：US12250818B2
公开(公告)日：2025-03-11
申请号：US17586682
申请日：2022-01-27
Applicant: Micron Technology, Inc.
Inventor： Pei Qiong Cheung , Zhixin Xu , Yuan Fang
Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
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公开(公告)号：US20240049468A1
公开(公告)日：2024-02-08
申请号：US18381791
申请日：2023-10-19
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , Dong Wang , Rui Zhang , Da Xing , Xiao Li , Pei Qiong Cheung , Xiao Zeng
Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
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公开(公告)号：US20220157850A1
公开(公告)日：2022-05-19
申请号：US17586682
申请日：2022-01-27
Applicant: Micron Technology, Inc.
Inventor： Pei Qiong Cheung , Zhixin Xu , Yuan Fang
IPC: H01L27/11582 , H01L27/11565
Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
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Patent Agency Ranking
公开(公告)号：US11271006B2
公开(公告)日：2022-03-08
申请号：US16704176
申请日：2019-12-05
Applicant: Micron Technology, Inc.
Inventor： Pei Qiong Cheung , Zhixin Xu , Yuan Fang
IPC: H01L27/11582 , H01L27/11565
Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
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公开(公告)号：US20250056802A1
公开(公告)日：2025-02-13
申请号：US18930589
申请日：2024-10-29
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , Dong Wang , Rui Zhang , Da Xing , Xiao Li , Pei Qiong Cheung , Xiao Zeng
Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
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公开(公告)号：US12167604B2
公开(公告)日：2024-12-10
申请号：US18381791
申请日：2023-10-19
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , Dong Wang , Rui Zhang , Da Xing , Xiao Li , Pei Qiong Cheung , Xiao Zeng
Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
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公开(公告)号：US20230069399A1
公开(公告)日：2023-03-02
申请号：US17446370
申请日：2021-08-30
Applicant: Micron Technology, Inc.
Inventor： Kailing Shih , Dong Wang , Pei Qiong Cheung
IPC: H01L23/00 , H01L27/11556 , H01L27/11582
Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers and the tiers arranged in decks. At least one live pillar, comprising a channel material, extends through the decks to a source/drain region. At least one source/drain contact also extends through the decks. In a transition area horizontally between the live pillar(s) and the source/drain contact(s), at least one dummy pillar extends through at least one of the decks. The dummy pillar(s) are separated from the source/drain region by at least one of the tiers of a lower of the decks. The dummy pillar(s) are also spaced from the source/drain contact(s). Additional microelectronic devices are also disclosed, as are related methods and electronic systems.
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公开(公告)号：US20220310642A1
公开(公告)日：2022-09-29
申请号：US17211580
申请日：2021-03-24
Applicant: Micron Technology, Inc.
Inventor： Shuangqiang Luo , Dong Wang , Rui Zhang , Da Xing , Xiao Li , Pei Qiong Cheung , Xiao Zeng
IPC: H01L27/11582 , H01L27/11556 , H01L27/11526 , H01L27/11573
Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
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