公开(公告)号：US6111286A

公开(公告)日：2000-08-29

申请号：US177786

申请日：1998-10-22

申请人： Min-hwa Chi ,  Chih Ming Chen

发明人： Min-hwa Chi ,  Chih Ming Chen

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7883

摘要： A flash memory cell formed on a semiconductor substrate is disclosed. The cell comprises: a p-well formed in the substrate; a gate structure formed atop the p-well, the gate structure including a control gate and a floating gate, the floating gate electrically isolated from the control gate and the semiconductor substrate by a thin dielectric layer; an n- base formed adjacent to a first edge of the gate structure and extending underneath the gate structure; a p+ structure formed within the n- base and adjacent to the first edge of the gate structure; and a n+ structure adjacent a second edge of the gate structure. With such a structure, it is possible to program the cell by band-to-band tunneling enhanced hot electrons generated at the p+ surface. The erase is performed by Fowler-Nordheim tunneling through the n- base region.

摘要翻译： 公开了一种形成在半导体衬底上的闪存单元。 该电池包括：在衬底中形成的p阱; 栅极结构形成在p阱的顶部，栅极结构包括控制栅极和浮置栅极，通过薄介电层与控制栅极和半导体衬底电隔离的浮置栅极; 形成在栅极结构的第一边缘附近并在栅极结构下方延伸的n-基极; 形成在所述n基极内且与所述栅极结构的第一边缘相邻的p +结构; 以及与栅极结构的第二边缘相邻的n +结构。 通过这样的结构，可以通过在p +表面产生的带对带隧穿增强的热电子对单元进行编程。 擦除由Fowler-Nordheim穿过n基区进行。

公开(公告)号：US06088259A

公开(公告)日：2000-07-11

申请号：US253322

申请日：1999-02-19

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C11/412 ,  G11C11/00

CPC分类号： G11C11/412

摘要： A SRAM cell is disclosed. The SRAM cell comprises: a first inverter having an input and an output; a second inverter having an input and an output, the output of the second inverter capacitively coupled to the input of the first inverter, the input of the second inverter capacitively coupled to the output of the first inverter; a first access transistor controlled by a wordline and connected between the output of the first inverter and a bitline; and a second access transistor controlled by the wordline and connected between the output of the second inverter and a complement to the bitline.

摘要翻译： 公开了一种SRAM单元。 SRAM单元包括：具有输入和输出的第一反相器; 具有输入和输出的第二反相器，与第一反相器的输入电容耦合的第二反相器的输出，与第一反相器的输出电容耦合的第二反相器的输入; 由字线控制并连接在第一反相器的输出端和位线之间的第一存取晶体管; 以及由字线控制并连接在第二反相器的输出和位线的补码之间的第二存取晶体管。

公开(公告)号：US6087690A

公开(公告)日：2000-07-11

申请号：US170863

申请日：1998-10-13

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/108

摘要： A single polysilicon DRAM cell is disclosed. The DRAM cell comprises: a deep n-well in a silicon substrate; a p-well within the deep n-well; a gate structure over and straddling the deep n-well and the p-well, the gate structure being a stack of a thin gate oxide layer and a conductive layer; and a n+ well within the p-well and adjacent to a sidewall of the gate structure. The p-well potential can be reset to -V.sub.cc /2 representing "0", and written to V.sub.cc /2 representing "1". The parasitic n-channel MOS with the p-well as the "body" will have a threshold voltage modulated by the p-well potential at V.sub.cc /2 and -V.sub.cc /2 for representing "1" and "0" states, respectively.

摘要翻译： 公开了单个多晶硅DRAM单元。 DRAM单元包括：硅衬底中的深n阱; 深井内的p井; 栅极结构在其上并跨越深n阱和p阱，栅极结构是薄栅极氧化物层和导电层的堆叠; 和p阱内的n +阱并且与栅极结构的侧壁相邻。 p阱电位可以复位为-Vcc / 2，表示“0”，并写入表示“1”的Vcc / 2。 具有p阱作为“体”的寄生n沟道MOS将分别由Vcc / 2和pcc阱的p阱电位调制阈值电压，并分别表示“1”和“0”状态。

公开(公告)号：US6025625A

公开(公告)日：2000-02-15

申请号：US258083

申请日：1999-02-25

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L29/7885 ,  G11C2216/10

摘要： A single-poly EEPROM cell comprising an inverter and a capacitive coupling area. The inverter is formed by: a p-well formed in a substrate; a gate structure formed atop the p-well and being formed from a thin gate oxide layer underneath a conductive layer; an n-base formed adjacent to a first edge of the gate structure and within the p-well; a p+ structure formed within the n-base; and a n+ structure adjacent a second edge of the gate structure and within the p-well. The capacitive coupling area is formed from a second p-well formed in the substrate and a floating gate, the floating gate formed from the conductive layer and capacitively coupled to the second p-well.

摘要翻译： 包括反相器和电容耦合区域的单个多晶EEPROM单元。 逆变器由以下部分形成：在衬底中形成的p阱; 形成在p阱顶上并由导电层下面的薄栅极氧化层形成的栅极结构; 形成在栅极结构的第一边缘附近并在p阱内的n基底; 在n基中形成的p +结构; 以及邻近门结构的第二边缘并且在p阱内的n +结构。 电容耦合区域由形成在衬底中的第二p阱和浮置栅极形成，浮置栅极由导电层形成并电容耦合到第二p阱。