摘要:
A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.
摘要:
The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
摘要:
A computer implemented method, system and computer program product for providing a waveform trace of a last plurality of cycles of a simulation prior to occurrence of an error in the simulation. A computer implemented method in a data processing system for providing a waveform trace for a last plurality of cycles of a simulation prior to occurrence of an error in the simulation includes storing history information relating to a last plurality of cycles of a simulation during running of the simulation. Responsive to an error occurring in the simulation, the simulation is stopped, and a waveform trace for the last plurality of cycles of the simulation is provided using the stored history information.