公开(公告)号：US20090228751A1

公开(公告)日：2009-09-10

申请号：US12125476

申请日：2008-05-22

申请人： Tilman Gloekler ,  Christoph Jaeschke ,  Thuyen Le ,  Martin Padeffke

发明人： Tilman Gloekler ,  Christoph Jaeschke ,  Thuyen Le ,  Martin Padeffke

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318536 ,  G01R31/318547

摘要： A method, structure and design system for performing logic built-in-self-test (LBIST) cycles on a semiconductor chip with a plurality of logic circuits and a plurality of storage elements connected serially to a number of LBIST stumps (pattern segments) between a pseudo-random-pattern generator (30) and a multiple-input-signature register. The semiconductor chip is subdivided into partitions, such that LBIST cycles may be run separately or in parallel for one or more partitions. The LBIST cycles may also be run separately or in parallel inter-connections between the partitions. The partitions to be tested are controlled by at least one corresponding clock signal, and the inter-connections to be tested are controlled by at least one corresponding clock signal.

摘要翻译： 一种用于在半导体芯片上执行逻辑内置自检（LBIST）周期的方法，结构和设计系统，其具有多个逻辑电路和多个存储元件，所述多个逻辑电路和多个存储元件串联连接到多个LBIST树桩（图案段）之间， 伪随机模式生成器（30）和多输入签名寄存器。 半导体芯片被细分为分区，使得LBIST周期可以针对一个或多个分区单独运行或并行运行。 LBIST循环也可以分开运行或在分区之间并行连接。 要测试的分区由至少一个对应的时钟信号控制，并且待测试的互连由至少一个相应的时钟信号控制。

公开(公告)号：US08055931B2

公开(公告)日：2011-11-08

申请号：US12246123

申请日：2008-10-06

申请人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

发明人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

IPC分类号： G06F1/04

CPC分类号： G06F1/12

摘要： A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

摘要翻译： 提供了一种用于在对准元件内的两个振荡器信号之间切换的方法。 根据该方法，选择两个振荡器信号之一作为第一主信号，以便在对准元件的输出处提供输出步进信号。 该方法包括当两个振荡器信号之间的开关发生时或当检测到第一主信号的故障时引入虚拟步进信号。 该方法还包括在开关的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成。

公开(公告)号：US07913136B2

公开(公告)日：2011-03-22

申请号：US12052844

申请日：2008-03-21

申请人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

发明人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/31855

摘要： The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps (10, 12) with the pseudo-random-pattern generator (26), deactivating the multiple-input-signature register (28), performing a functional update in order to propagate legal values into those storage elements (16), which require constrained values, activating or resetting (51) the multiple-input-signature register (28), and setting or programming a start value in a counter (42) for activating a loop back circuit (34) in order to avoid an overwriting of the well-constrained values in the storage elements (16).

摘要翻译： 本发明涉及一种用于在电子电路上执行逻辑内置自检（LBIST）的方法，该电子电路具有多个逻辑电路（18,20,22,24）和串行连接到 伪随机模式生成器（26）和多输入签名寄存器（28）之间的多个LBIST树桩（10,12），其中至少一个约束逻辑电路（18）需要约束值作为输入信号。 所述方法包括以下步骤：用伪随机模式生成器（26）扫描LBIST树桩（10,12），去激活多输入签名寄存器（28），执行功能更新以便传播合法值 进入需要约束值的那些存储元件（16），激活或复位（51）多输入签名寄存器（28），以及在用于激活环回电路的计数器（42）中设置或编程起始值（ 34），以避免在存储元件（16）中覆盖良好约束的值。

公开(公告)号：US20090100283A1

公开(公告)日：2009-04-16

申请号：US12246123

申请日：2008-10-06

申请人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

发明人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.

摘要翻译： 一种用于在对准元件内切换两个振荡器信号的方法，其中两个振荡器信号之一被选择为第一主信号，以便在对准元件的输出处提供输出步进信号。 所述方法包括以下步骤：当发生两个振荡器信号之间的切换时或当检测到第一主信号的故障时，引入虚拟步进信号; 在切换的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成; 在主信号发生故障的情况下将虚拟步进信号发送到对准元件的输出，直到作为新的主信号切换到另一个振荡器信号，或者直到第一主信号再次变为有效。

公开(公告)号：US20080250289A1

公开(公告)日：2008-10-09

申请号：US12052844

申请日：2008-03-21

申请人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

发明人： Tilman Gloekler ,  Michael Kugel ,  Thuyen Le ,  Matthias Woehrle

IPC分类号： G01R31/28

CPC分类号： G01R31/31716 ,  G01R31/31855

摘要： The present invention relates to a method for performing a logic built-in self-test (LBIST) on an electronic circuit with a plurality of logic circuits (18, 20, 22, 24) and storage elements (14, 16) connected serially to a number of LBIST stumps (10, 12) between a pseudo-random-pattern generator (26) and a multiple-input-signature register (28), wherein at least one constrained logic circuit (18) requires constrained values as input signals. Said method comprises the following steps: scanning the LBIST stumps (10, 12) with the pseudo-random-pattern generator (26), deactivating the multiple-input-signature register (28), performing a functional update in order to propagate legal values into those storage elements (16), which require constrained values, activating or resetting (51) the multiple-input-signature register (28), and setting or programming a start value in a counter (42) for activating a loop back circuit (34) in order to avoid an overwriting of the well-constrained values in the storage elements (16).

摘要翻译： 本发明涉及一种用于在电子电路上执行逻辑内置自检（LBIST）的方法，该电子电路具有多个逻辑电路（18,20,22,24）和串行连接到 伪随机模式生成器（26）和多输入签名寄存器（28）之间的多个LBIST树桩（10,12），其中至少一个约束逻辑电路（18）需要约束值作为输入信号。 所述方法包括以下步骤：用伪随机模式生成器（26）扫描LBIST树桩（10,12），去激活多输入签名寄存器（28），执行功能更新以便传播合法值 进入需要约束值的那些存储元件（16），激活或复位（51）多输入签名寄存器（28），以及在用于激活环回电路的计数器（42）中设置或编程起始值（ 34），以避免在存储元件（16）中覆盖良好约束的值。

公开(公告)号：US20080172508A1

公开(公告)日：2008-07-17

申请号：US11972648

申请日：2008-01-11

申请人： Tilman Gloekler ,  Thuyen Le ,  Thomas Pflueger ,  Matthias Woehrlc

发明人： Tilman Gloekler ,  Thuyen Le ,  Thomas Pflueger ,  Matthias Woehrlc

IPC分类号： G06F13/372

CPC分类号： G06F13/372

摘要： The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.

摘要翻译： 本发明涉及一种用于仲裁主人的请求以授权对共享资源的访问的方法，其中每个主人具有单独的权重。 该方法包括以下步骤：根据主机的权重向主机分配时隙，将当前时隙索引（32）映射到重新排序索引（30），从N个主机接收多个请求，将请求重新排序 根据重新排序索引（30）的请求向量（14），在请求向量（14）中搜索预定的逻辑值，根据请求向量（14）中找到的逻辑值的索引生成授权向量（18） ），根据所述重排序索引（30）将所述授权向量（18）逆序排列到输出许可向量（22）中，并且基于当前时隙索引（30）计算新的时隙索引（32），以及 授权向量（18）。 此外，本发明涉及一种用于执行该方法的系统。

公开(公告)号：US20120151423A1

公开(公告)日：2012-06-14

申请号：US13284489

申请日：2011-10-28

申请人： Jason R. Baumgartner ,  Tilman Gloekler ,  Christoph Jaeschke ,  Ralf Ludewig

发明人： Jason R. Baumgartner ,  Tilman Gloekler ,  Christoph Jaeschke ,  Ralf Ludewig

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.

摘要翻译： 一种用于执行电子电路设计中的属性的形式验证的改进方法包括：在寄存器传送级别指定电子电路设计中的至少一个安全属性，根据可配置的方式将逻辑锥的边界设置为起始级别 结构设计标准，基于至少一个指定的安全属性和设定的边界，从电子电路设计中提取逻辑锥，在逻辑锥上执行形式验证工具，以验证至少一个指定的属性， 根据可配置结构设计标准的逻辑锥，并且如果验证结果不满足至少一个安全属性，则执行在新的逻辑锥上的提取和执行。

公开(公告)号：US20080167853A1

公开(公告)日：2008-07-10

申请号：US11621361

申请日：2007-01-09

申请人： Matthew E. Fernsler ,  Tilman Gloekler ,  Sanjay Gupta ,  Christopher J. Spandikow ,  Todd Swanson

发明人： Matthew E. Fernsler ,  Tilman Gloekler ,  Sanjay Gupta ,  Christopher J. Spandikow ,  Todd Swanson

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318357 ,  G06F11/261

摘要： A general purpose computational resource is provided for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is provided for: storing test patterns, a description of integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns

摘要翻译： 提供通用计算资源用于执行系统的通用操作。 专用计算资源与通用计算资源相连。 专用计算资源用于：存储测试模式，集成电路的描述以及用于测试集成电路的硬件描述; 以及执行用于模拟所述硬件对所述集成电路的测试的响应于所述测试模式的软件

公开(公告)号：US07386775B2

公开(公告)日：2008-06-10

申请号：US11206846

申请日：2005-08-18

申请人： Parag Birmiwal ,  Tilman Gloekler ,  Klaus Heinzelmann ,  Johannes Koesters

发明人： Parag Birmiwal ,  Tilman Gloekler ,  Klaus Heinzelmann ,  Johannes Koesters

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318583

摘要： Methods, apparatus, and products are disclosed for scan verification for a simulated device under test (‘DUT’), the DUT having scan chains, scan inputs, and scan outputs that include verifying correct data entry from the scan inputs of the DUT into the beginning of the scan chain, verifying correct propagation of scan data in the scan chain between the scan inputs and the scan outputs, verifying correct data output from the end of the scan chain to the scan outputs, and leak testing the scan chain with undetermined states for scan cells in the scan chain.

摘要翻译： 公开了用于待测仿真设备（'DUT'）的扫描验证的方法，装置和产品，DUT具有扫描链，扫描输入和扫描输出，其包括验证从DUT的扫描输入的正确数据输入到 扫描链的开始，验证扫描输入和扫描输出之间的扫描链中的扫描数据的正确传播，验证从扫描链的末端输出到扫描输出的正确数据，并对具有未确定状态的扫描链进行泄漏测试 用于扫描链中的扫描单元。

公开(公告)号：US07350124B2

公开(公告)日：2008-03-25

申请号：US11252512

申请日：2005-10-18

申请人： Tilman Gloekler ,  Christian Habermann ,  Naoki Kiryu ,  Joachim Kneisel ,  Johannes Koesters

发明人： Tilman Gloekler ,  Christian Habermann ,  Naoki Kiryu ,  Joachim Kneisel ,  Johannes Koesters

IPC分类号： G06F11/00

CPC分类号： G06F17/5022 ,  G01R31/318357

摘要： The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

摘要翻译： 本发明提供一种用于对TTP-LBIST应用外部时钟和数据模式的方法，装置和计算机程序产品。 在仿真器中设置了被测逻辑的仿真模型。 接下来，用户设置外部LBIST块，其包括预先验证的内部时钟和数据模式逻辑，并将该块连接到仿真模型中的逻辑。 内部时钟和数据模式逻辑提供了用于LBIST的OPCG模式的输入模式。 该内部时钟和数据模式逻辑已经通过设计工作进行了验证。 因此，内部模式发生器成为模拟模型中的外部模式发生器。 外部LBIST块应用外部时钟和数据模式，随后用户接收并处理这些输出模式以确定逻辑是否正常工作。