公开(公告)号：US09837413B2

公开(公告)日：2017-12-05

申请号：US15041593

申请日：2016-02-11

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/786 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/82 ,  H01L29/10 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/528 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78654

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US09614367B2

公开(公告)日：2017-04-04

申请号：US14475683

申请日：2014-09-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H01L29/74

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L27/0277 ,  H01L29/7436 ,  H02H9/044

Abstract: A device includes a transistor configured for operating in a hybrid mode, an element configured for generating and injecting a current into the substrate of the transistor in the presence of an ESD pulse, and a thyristor triggerable at least by the element.

公开(公告)号：US20150077888A1

公开(公告)日：2015-03-19

申请号：US14475683

申请日：2014-09-03

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0262 ,  H01L27/0277 ,  H01L29/7436 ,  H02H9/044

Abstract: A device includes a transistor configured for operating in a hybrid mode, an element configured for generating and injecting a current into the substrate of the transistor in the presence of an ESD pulse, and a thyristor triggerable at least by the element.

Abstract translation: 一种器件包括被配置为以混合模式操作的晶体管，被配置为在存在ESD脉冲的情况下产生并注入到晶体管的衬底中的元件以及至少可被该元件触发的晶闸管。

公开(公告)号：US20130120049A1

公开(公告)日：2013-05-16

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/72

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。