公开(公告)号：USD685689S1

公开(公告)日：2013-07-09

申请号：US29404410

申请日：2011-10-20

申请人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

设计人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

公开(公告)号：USD674326S1

公开(公告)日：2013-01-15

申请号：US29404412

申请日：2011-10-20

申请人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

设计人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

公开(公告)号：USD670417S1

公开(公告)日：2012-11-06

申请号：US29404416

申请日：2011-10-20

申请人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

设计人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

公开(公告)号：USD669826S1

公开(公告)日：2012-10-30

申请号：US29404399

申请日：2011-10-20

申请人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

设计人： Christopher Svensson ,  Paul Campbell ,  Paul Wraith

公开(公告)号：US20060166909A1

公开(公告)日：2006-07-27

申请号：US10518470

申请日：2003-06-20

申请人： Moshe Szyf ,  Paul Campbell

发明人： Moshe Szyf ,  Paul Campbell

IPC分类号： A61K48/00 ,  C12Q1/68 ,  C07H21/02

CPC分类号： C12Q1/6809 ,  A61K38/00 ,  C12N15/1137 ,  C12N2310/111 ,  C12N2310/315 ,  C12N2310/317 ,  C12N2310/321 ,  C12N2310/341 ,  C12N2310/345 ,  C12N2310/346 ,  C12Q1/6886 ,  C12Q2600/142 ,  C12Q2600/154 ,  C12Q2600/158 ,  C12N2310/3521

摘要： Oligonucleotide inhibitors that inhibit expression of a mammalian MBD2/DNA demethylase (MBD2/dMTase) are provided. The oligonucleotide inhibitors can be used to inhibit the growth or proliferation of tumour cells in vitro and in vivo. The use of the oligonucleotide inhibitors in the treatment of cancer and methods of identifying potential target genes for cancer therapy or diagnosis using the oligonucleotide inhibitors are also provided.

摘要翻译： 提供抑制哺乳动物MBD2 / DNA脱甲基酶（MBD2 / dMTase）表达的寡核苷酸抑制剂。 寡核苷酸抑制剂可用于在体外和体内抑制肿瘤细胞的生长或增殖。 还提供了寡核苷酸抑制剂在治疗癌症中的用途以及使用寡核苷酸抑制剂鉴定癌症治疗或诊断的潜在靶基因的方法。

公开(公告)号：US07047394B1

公开(公告)日：2006-05-16

申请号：US09666110

申请日：2000-09-20

申请人： Korbin S. Van Dyke ,  Paul Campbell ,  Don Alan Van Dyke

发明人： Korbin S. Van Dyke ,  Paul Campbell ,  Don Alan Van Dyke

IPC分类号： G06F9/30

CPC分类号： G06F9/3822 ,  G06F9/30123 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

摘要： A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set. The CISC instruction set provides accessibility to only a subset of the registers of the general register file, intermediate results of instructions of the instruction set being stored in registers of the general register file that are inaccessible in the CISC instruction set.

摘要翻译： 公开了一种计算机。 计算机具有寄存器的通用寄存器文件，RISC指令解码器和CISC指令解码器。 RISC指令解码器被暴露用于执行RISC指令集中的用户状态程序，作为具有固定长度指令的指令集和加载/存储/操作组织。 硬件CISC指令解码器被暴露以由CISC指令集中的用户状态程序执行，作为具有可变长度指令的指令集和具有多个副作用的许多指令。 CISC解码器被设计为对计算机的指令集的一部分进行解码，并且将解码的指令递送到被设计为执行RISC指令解码器和CISC指令解码器的输出的指令执行流水线。 软件仿真器被编程为实现指令集的剩余部分。 CISC指令集仅提供对通用寄存器文件的寄存器的子集的可访问性，指令集的指令的中间结果存储在通用寄存器堆的寄存器中，该寄存器在CISC指令集中是不可访问的。

公开(公告)号：US20060065952A1

公开(公告)日：2006-03-30

申请号：US11239438

申请日：2005-09-20

申请人： John Boos ,  Brian Bennett ,  Paul Campbell ,  Richard Magno

发明人： John Boos ,  Brian Bennett ,  Paul Campbell ,  Richard Magno

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/201 ,  H01L29/205 ,  H01L29/7371

摘要： This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.

公开(公告)号：US20050133775A1

公开(公告)日：2005-06-23

申请号：US10740697

申请日：2003-12-18

申请人： Paul Campbell

发明人： Paul Campbell

IPC分类号： E04H17/06 ,  E04H17/02

CPC分类号： E04H17/066

摘要： A retaining-locking system for chain link fence slats includes specially notched fence slat elements having a pointed upper or lower end. The slat elements are sized and shaped to be interwoven between consecutive links of a chain link fence. A retaining-locking strip is formed of resilient material, and has an inner surface and an outer surface and at least one securing protrusion. The securing protrusion is sized and shaped to fit slidably within the notch. The protrusion is located on the outer surface of the strip. When the slat elements are interwoven into between consecutive links of a chain link fence with each of the notches aligned with one another, the retaining-locking strip inserted between the slat elements and the links, with the securing protrusion disposed within the slats, the strip will urge the slats toward the links, thereby retaining the slats within the chain link fence.

摘要翻译： 用于链条篱笆板条的保持锁定系统包括具有尖的上端或下端的特别缺口的栅栏板条件。 板条元件的尺寸和形状被设计成在链节栅栏的连续链节之间交织。 保持锁定条由弹性材料形成，并且具有内表面和外表面以及至少一个固定突起。 固定突起的尺寸和形状可滑动地配合在凹口内。 突起位于条的外表面上。 当板条元件交织在链节栏杆的连续链节之间，每个凹口彼此对准时，保持锁定条插入在板条元件和链节之间，固定突起设置在板条内，条带 将推动板条朝向连杆，从而将板条保持在链条围栏内。

公开(公告)号：US06526459B1

公开(公告)日：2003-02-25

申请号：US09438573

申请日：1999-11-10

申请人： Paul Campbell ,  Ali Alasti

发明人： Paul Campbell ,  Ali Alasti

IPC分类号： G06F1314

CPC分类号： G06F12/1027 ,  G06F12/0292 ,  G06F12/1081 ,  G06F2212/206

摘要： A method and apparatus is provided for providing communication with input/output devices without being bound by the limitations of an existing input/output bus while still providing compatibility with software intended to communicate with input/output devices using the existing input/output bus. The software image of the input/output devices as being associated with the input/output bus is preserved, but a technique is provided to allow communication with the input/output devices to bypass the existing input/output bus. A translation lookaside buffer is utilized to remap accesses to an internal input/output device from virtual address space for input/output-bus-based input/output devices to physical address space for the internal input/output device. Circuitry for interfacing with the input/output devices separately from the existing input/output bus may be fabricated as a single integrated circuit device along with other system components, such as a central processing unit.

摘要翻译： 提供了一种用于提供与输入/输出设备的通信的方法和装置，而不受现有输入/输出总线的限制的约束，同时仍然提供与旨在使用现有输入/输出总线与输入/输出设备通信的软件的兼容性。 输入/输出设备的与输入/输出总线相关联的软件映像被保留，但是提供了一种技术来允许与输入/输出设备通信以绕过现有的输入/输出总线。 翻译后备缓冲器用于从用于基于输入/输出总线的输入/输出设备的虚拟地址空间到用于内部输入/输出设备的物理地址空间的对内部输入/输出设备的访问重新映射。 与现有输入/输出总线分开的与输入/输出设备进行接口的电路可以与其他系统组件（如中央处理单元）一起制造为单个集成电路设备。

公开(公告)号：US06418524B1

公开(公告)日：2002-07-09

申请号：US09473154

申请日：1999-12-28

申请人： Korbin Van Dyke ,  Paul Campbell

发明人： Korbin Van Dyke ,  Paul Campbell

IPC分类号： G06F1210

CPC分类号： G06F12/1036 ,  G06F12/109

摘要： A method and apparatus for dependent segmentation and paging processing within a computer system include processing that begins by determining context of an operation supported by a native operating system. The context of an operation may correspond to performing an operation that is a native operating system operation or may be a legacy operating system operation. The processing then continues by setting within a corresponding segment descriptor a paging enable bit for a given segment that corresponds to the operation when the context of the operation corresponds to a legacy operating system. The setting of the paging enable bit is done in accordance with the processing of the native operating system. The processing then continues by processing the segment descriptor via segmentation processing in accordance with the legacy operating system to obtain a linear address. With the paging enable bitd, the linear address is processed to obtain a physical address.

摘要翻译： 用于在计算机系统内进行依赖分割和寻呼处理的方法和装置包括通过确定由本地操作系统支持的操作的上下文开始的处理。 操作的上下文可以对应于执行作为本机操作系统操作的操作，或者可以是传统操作系统操作。 然后，当操作的上下文对应于传统操作系统时，通过在相应的段描述符内设置对应于操作的给定段的寻呼使能位来继续处理。 寻呼使能位的设置是根据本地操作系统的处理完成的。 然后通过根据传统操作系统的分段处理来处理段描述符来继续处理以获得线性地址。 通过寻呼使能位d，处理线性地址以获得物理地址。