公开(公告)号：US20100132467A1

公开(公告)日：2010-06-03

申请号：US12509360

申请日：2009-07-24

申请人： Sang Choon Ko ,  Chi Hoon Jun ,  Byoung Gon Yu ,  Chang Auck Choi

发明人： Sang Choon Ko ,  Chi Hoon Jun ,  Byoung Gon Yu ,  Chang Auck Choi

IPC分类号： G01P15/125 ,  H01L21/306

CPC分类号： G01P15/0802 ,  G01H11/06 ,  G01P1/023 ,  G01P15/125 ,  H04R19/005

摘要： Provided is a high-sensitivity MEMS-type z-axis vibration sensor, which may sense z-axis vibration by differentially shifting an electric capacitance between a doped upper silicon layer and an upper electrode from positive to negative or vice versa when center mass of a doped polysilicon layer is moved due to z-axis vibration. Particularly, since a part of the doped upper silicon layer is additionally connected to the center mass of the doped polysilicon layer, and thus an error made by the center mass of the doped polysilicon layer is minimized, it may sensitively respond to weak vibration of low frequency such as seismic waves. Accordingly, since the high-sensitivity MEMS-type z-axis vibration sensor sensitively responds to a small amount of vibration in a low frequency band, it can be applied to a seismograph sensing seismic waves of low frequency which have a very small amount of vibration and a low vibration speed. Moreover, since the high-sensitivity MEMS-type z-axis vibration sensor has a higher vibration sensibility than MEMS-type z-axis vibration sensor of the same size, it can be useful in electronic devices which are gradually decreasing in size.

摘要翻译： 提供了一种高灵敏度的MEMS型z轴振动传感器，其可以通过将掺杂的上硅层和上电极之间的电容从正向或者反向偏移来感测z轴振动，当中心质量为 掺杂多晶硅层由于z轴振动而移动。 特别地，由于掺杂的上硅层的一部分另外连接到掺杂多晶硅层的中心质量块，因此由掺杂多晶硅层的中心质量造成的误差最小化，可以敏感地响应低的振动弱 频率如地震波。 因此，由于高灵敏度的MEMS型z轴振动传感器对低频带中的少量振动敏感地作出响应，因此可以应用于地震仪中，以便感测具有极小振动频率的低频地震波 和低振动速度。 此外，由于高灵敏度的MEMS型z轴振动传感器具有比相同尺寸的MEMS型z轴振动传感器更高的振动灵敏度，所以在逐渐减小的电子设备中是有用的。

公开(公告)号：US20090146058A1

公开(公告)日：2009-06-11

申请号：US12182496

申请日：2008-07-30

申请人： Ho Jun RYU ,  Woo Seok Yang ,  Seong Mok Cho ,  Sang Hoon Cheon ,  Byoung Gon Yu ,  Chang Auck Choi

发明人： Ho Jun RYU ,  Woo Seok Yang ,  Seong Mok Cho ,  Sang Hoon Cheon ,  Byoung Gon Yu ,  Chang Auck Choi

IPC分类号： G01J5/10 ,  C01B33/06

CPC分类号： G01J5/20 ,  C22C1/04 ,  C23C14/14 ,  C23C14/3464

摘要： Provided are resistive materials for a microbolometer, a method for preparation of resistive materials and a microbolometer containing the resistive materials. The resistive materials for the microbolometer include an alloy of silicon and antimony or an alloy of silicon, antimony and germanium, which has a high TCR and a low resistance.

摘要翻译： 提供了用于微电热计的电阻材料，用于制备电阻材料的方法和包含电阻材料的微电热计。 用于微热辐射计的电阻材料包括硅和锑的合金或硅，锑和锗的合金，其具有高TCR和低电阻。

公开(公告)号：US06887772B2

公开(公告)日：2005-05-03

申请号：US10721970

申请日：2003-11-24

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H05B33/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L27/1203

摘要： The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

摘要翻译： 本发明涉及形成在SOI衬底上的高电压器件和低电压器件的结构及其制造方法，其特征在于SOI衬底中硅器件区域的低电压器件区域较高 比高压器件区域逐步，并且形成高压器件的硅器件​​区域的厚度等于低压器件中的源极和漏极的杂质的结深度。 因此，SOI衬底中的硅器件区域被分成高压区域和低电压区域，并且通过氧化生长方法在其间形成步骤，使得可以制造具有低结电容的高电压器件，并且低电压 与传统CMOS工艺兼容的器件和器件特性也可以同时进行。

公开(公告)号：US06411542B1

公开(公告)日：2002-06-25

申请号：US09966112

申请日：2001-10-01

申请人： Yil Suk Yang ,  Byoung Gon Yu ,  In Kyu You ,  Won Jae Lee ,  Kyoung Ik Cho

发明人： Yil Suk Yang ,  Byoung Gon Yu ,  In Kyu You ,  Won Jae Lee ,  Kyoung Ik Cho

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory device including a single ferroelectric transistor that one unit memory cell is independently selected and programmed, when the unit memory cell is programmed for “the first state” or “the second state” by applying a DC bias voltage to the single ferroelectric transistor's gate and well. In addition, the ferroelectric memory device can be applied with normal power level Vdd and GND. The ferroelectric memory device includes a plurality of unit memory cells which are arranged in a matrix, by crossing at least one word line in a column direction with a plurality of bit lines and source lines in a row direction and is connected between the source line and the bit line.

摘要翻译： 当单位存储单元被编程为“第一状态”或“第二状态”时，包括单个存储单元被独立地选择和编程的单个铁电晶体管的铁电存储器件通过将DC偏置电压施加到单个铁电晶体管 门和井。 此外，铁电存储器件可以应用正常的功率电平Vdd和GND。 铁电存储器件包括多个单元存储单元，它们以矩阵形式布置，使列方向上的至少一个字线与行方向上的多个位线和源极线相交，并连接在源极线和 位线。