公开(公告)号：US06650567B1

公开(公告)日：2003-11-18

申请号：US08213004

申请日：1994-03-14

申请人： Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

发明人： Sung-Hee Cho ,  Sang-Ki Hwang ,  Hyong-Gon Lee

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C17/123

摘要： A nonvolatile semiconductor integrated circuit having a cell array consisting of a plurality of memory strings each having first to N-th (N=2, 3, 4, . . . ) memory cell transistors of a NAND structure includes a plurality of first string select transistors connected in series to the first memory cell transistor, and a plurality of second string select transistors connected in series to the N-th memory cell transistor. One of the string select transistors serially connected to the first and N-th memory cell transistors has a control terminal connected to a ground connecting point, thus to have a ground select function as well as a string select function.

摘要翻译： 具有由NAND结构的第一至第N（N = 2,3,4 ...）个存储单元晶体管组成的多个存储串组成的单元阵列的非易失性半导体集成电路包括多个第一串选择 与第一存储单元晶体管串联连接的晶体管，以及与第N个存储单元晶体管串联连接的多个第二串选择晶体管。 串联连接到第一和第N存储单元晶体管的串选择晶体管之一具有连接到接地连接点的控制端子，从而具有接地选择功能以及串选择功能。

公开(公告)号：US5434814A

公开(公告)日：1995-07-18

申请号：US132175

申请日：1993-10-06

申请人： Sung-Hee Cho ,  Kang-Deog Suh ,  Hyong-Gon Lee ,  Jae-Yeong Do

发明人： Sung-Hee Cho ,  Kang-Deog Suh ,  Hyong-Gon Lee ,  Jae-Yeong Do

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04 ,  H01L27/00 ,  G11C11/40

CPC分类号： G11C29/822

摘要： A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

摘要翻译： 具有缺陷修复功能的掩模ROM存储对应于缺陷存储单元的地址信号，然后根据存储的地址信号是否与外部提供的地址信号相同，选择性地激活冗余行解码器或行解码器。 掩模ROM包括通过在字线方向上分组以行和列排列的多个只读存储器单元形成的第一和第二存储单元阵列; 第一和第二行解码器，用于组合外部提供的行地址信号，以选择性地驱动第一和第二存储单元阵列的字线; 以及行解码器选择器，用于根据包括第一存储单元阵列的缺陷存储单元的行块存储其中的地址信号，以便在外部行地址信号等于第一行解码器时使第一行解码器失活，并激活第二行解码器 存储在行解码器选择器中的地址信号。

公开(公告)号：US5036272A

公开(公告)日：1991-07-30

申请号：US357989

申请日：1989-05-30

申请人： Sung-Hee Cho ,  Jae-Young Do ,  Jin-Ki Kim

发明人： Sung-Hee Cho ,  Jae-Young Do ,  Jin-Ki Kim

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/31701

摘要： A plural test mode selection circuit in a semiconductor device capable of extending the number of option modes, e.g., up to 16 option modes by adding a high voltage sensing circuit 15 to any one of a plurality of input pads and by arranging a master decoder 25 and a slave decoder 20 each coupled to a plurality of buffer circuits 11-14, as well as a mode selector 30 and a plurality of address/control pads 5-9, and then an output of a high voltage sensing circuit 15 and respective outputs of the master decoder 25 and a slave decoder 20 are combined together at a mode selector 30, so that a plurality of test modes selection is possible therefrom. In addition, the invention also has an advantage capable of testing a chip even after it has been made into a package because of utilizing the address/control pad used in a general read/write operation.

摘要翻译： 一种半导体装置中的多个测试模式选择电路，其能够通过向多个输入焊盘中的任一个添加高电压感测电路15并且通过布置主解码器25来扩展选项模式的数量，例如多达16种选择模式 以及从属解码器20，每个耦合到多个缓冲电路11-14，以及模式选择器30和多个地址/控制板5-9，然后是高电压感测电路15的输出和相应的输出 主解码器25和从解码器20在模式选择器30处组合在一起，使得可以从其中选择多个测试模式。 此外，本发明还具有能够在由于利用一般的读/写操作中使用的地址/控制板而将芯片制成封装后进行测试的优点。