公开(公告)号：US20190187209A1

公开(公告)日：2019-06-20

申请号：US16284465

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/3183

CPC classification number: G01R31/31723 ,  G01R31/2896 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/318513 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

公开(公告)号：US10324125B2

公开(公告)日：2019-06-18

申请号：US15790597

申请日：2017-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/28 ,  H01L23/522 ,  G01R31/3185 ,  H01L21/66 ,  H01L23/538 ,  H01L23/48

Abstract: An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.

公开(公告)号：US10281526B2

公开(公告)日：2019-05-07

申请号：US16003858

申请日：2018-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US10267856B2

公开(公告)日：2019-04-23

申请号：US15845339

申请日：2017-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Baher S. Haroun

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/04 ,  G01R31/3177 ,  G01R31/3185

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

公开(公告)号：US10267854B2

公开(公告)日：2019-04-23

申请号：US15655248

申请日：2017-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317 ,  H01L23/00

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

公开(公告)号：US20190064263A1

公开(公告)日：2019-02-28

申请号：US16175066

申请日：2018-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US10209305B2

公开(公告)日：2019-02-19

申请号：US16026721

申请日：2018-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/28

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

公开(公告)号：US10197628B2

公开(公告)日：2019-02-05

申请号：US15499362

申请日：2017-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G06F13/14 ,  G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

公开(公告)号：US20180364305A1

公开(公告)日：2018-12-20

申请号：US16108761

申请日：2018-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318536 ,  G01R31/318572 ,  G01R31/318577

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

公开(公告)号：US10151795B2

公开(公告)日：2018-12-11

申请号：US15591770

申请日：2017-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.