FAIL-SAFE FOR SHARED PIN
    51.
    发明申请

    公开(公告)号:US20190123543A1

    公开(公告)日:2019-04-25

    申请号:US16227656

    申请日:2018-12-20

    Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

    Fail-Safe For Shared Pin
    53.
    发明申请

    公开(公告)号:US20170288391A1

    公开(公告)日:2017-10-05

    申请号:US15087089

    申请日:2016-03-31

    CPC classification number: H02H3/20

    Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

    LOW DROPOUT VOLTAGE REGULATOR CIRCUITS
    54.
    发明申请
    LOW DROPOUT VOLTAGE REGULATOR CIRCUITS 有权
    低压差电压调节器电路

    公开(公告)号:US20150234404A1

    公开(公告)日:2015-08-20

    申请号:US14183739

    申请日:2014-02-19

    CPC classification number: G05F1/575

    Abstract: In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal.

    Abstract translation: 在一个实施例中,公开了一种电压调节器。 电压调节器电路包括开关,第一反馈电路和第二反馈电路。 该开关被配置为在第一终端处接收输入信号,并在第二终端处接收错误信号,并且被配置为在第三终端处产生输出信号。 第一反馈电路包括第一晶体管和第二晶体管,其被配置为响应于输出信号和参考信号之间的差异来控制开关的第二端处的误差信号。 第二反馈电路被配置为感测误差信号并在第二节点和第四节点处产生尾电流,以在第一晶体管和第二晶体管中分别维持基本上相等的电流,从而使输出信号的电压基本上 等于参考信号的电压。

    Input offset control
    55.
    发明授权
    Input offset control 有权
    输入偏移控制

    公开(公告)号:US09083232B1

    公开(公告)日:2015-07-14

    申请号:US14162470

    申请日:2014-01-23

    Inventor: Nitin Agarwal

    Abstract: Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.

    Abstract translation: 公开了用于输入偏移控制的若干电路和方法。 在一个实施例中,输入偏移控制电路包括第一输入电路和第二输入电路。 第一输入电路被配置为在第一共模电压范围内工作,被配置为提供第一输入电流,并且被配置为在第一共模电压范围内的电压电平的变化或之后改变第一输入电流。 第二输入电路耦合到第一输入电路,并且被配置为在第二共模电压范围内工作,被配置为提供第二输入电流,并且被配置为基于第二公共电压中的电压电平的变化来改变第二输入电流 模式电压范围。 在增加共模电压或随后增加共模电压时,第一输入电流减小并且第二输入电流增加。

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