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公开(公告)号：US10317925B2
公开(公告)日：2019-06-11
申请号：US15473209
申请日：2017-03-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Rajavelu Thinakaran , Sumit Dubey
Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.
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公开(公告)号：US10211621B2
公开(公告)日：2019-02-19
申请号：US15087089
申请日：2016-03-31
Applicant: Texas Instruments Incorporated
Inventor： Sumit Dubey , Nitin Agarwal
IPC: H02H3/20
Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
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公开(公告)号：US12003243B2
公开(公告)日：2024-06-04
申请号：US17232174
申请日：2021-04-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Jasjot Singh Chadha
Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
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公开(公告)号：US09866237B1
公开(公告)日：2018-01-09
申请号：US15593618
申请日：2017-05-12
Applicant: Texas Instruments Incorporated
Inventor： Rajavelu Thinakaran , Sumit Dubey
CPC classification number: H03M3/422 , H03H19/004 , H03M1/1245 , H03M3/45
Abstract: Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.
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公开(公告)号：US20240213935A1
公开(公告)日：2024-06-27
申请号：US18088091
申请日：2022-12-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Rejin Kanjavalappil Raveendranathath , Shaik Asif Basha
CPC classification number: H03F3/2173 , H03F1/3205 , H03F2200/03 , H03F2200/351
Abstract: Examples of amplifiers and components thereof are configured to adjust the OFF-pulse widths of a high-duty cycle pulse width modulated (PWM) output signal and the ON-pulse widths of a low-duty cycle PWM output signal. Such control is carried out using high- and low-side (HS and LS) detectors. The HS detector coupled to the control terminal of an HS transistor detects when the gate-to-source voltage (Vgs) of the HS transistor drops below a threshold and outputs an HS detection signal to adjust the OFF-pulse widths of the high-duty cycle PWM output signal. An LS detector coupled to the control terminal of an LS transistor detects when the Vgs of the LS transistor drops below the threshold and outputs a LS detection signal to adjust the ON-pulse widths of the low-duty cycle PWM output signal.
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Patent Agency Ranking
公开(公告)号：US11139648B2
公开(公告)日：2021-10-05
申请号：US16227656
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Nitin Agarwal
IPC: H02H3/20
Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
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公开(公告)号：US11012058B2
公开(公告)日：2021-05-18
申请号：US16868104
申请日：2020-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Jasjot Singh Chadha
Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
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公开(公告)号：US20240223206A1
公开(公告)日：2024-07-04
申请号：US18147183
申请日：2022-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkata Ramanan Ramamurthy , Sumit Dubey , Jasjot Singh Chadha , Lokesh Kumar Botcha
Abstract: Examples of amplifiers and associated control blocks control analog and digital gains of such an amplifier to maintain a ripple voltage at the input/virtual terminals of an internal integrator below an upper limit. Such an example amplifier comprises digital and analog processing blocks. The digital processing block receives a digital audio signal and also includes a digital gain component. The analog processing block includes an analog gain component and an output stage having a supply voltage terminal. A boost controller receives the digital audio signal, and has a digital output and a boost voltage output to output a boost voltage. A digital controller receives the digital audio signal, and has a first digital input coupled to the digital output of the boost controller and a second digital input to receive a measurement value indicative of the outputted boost voltage. Based on its inputs, the digital controller controls the digital and analog gain components.
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公开(公告)号：US20190123543A1
公开(公告)日：2019-04-25
申请号：US16227656
申请日：2018-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Nitin Agarwal
IPC: H02H3/20
Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
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公开(公告)号：US20170288391A1
公开(公告)日：2017-10-05
申请号：US15087089
申请日：2016-03-31
Applicant: Texas Instruments Incorporated
Inventor： Sumit Dubey , Nitin Agarwal
IPC: H02H3/20
CPC classification number: H02H3/20
Abstract: An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.
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