公开(公告)号：US10297690B2

公开(公告)日：2019-05-21

申请号：US15725091

申请日：2017-10-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Liang-Yi Chen ,  Wen-Chu Hsiao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

公开(公告)号：US10269648B1

公开(公告)日：2019-04-23

申请号：US15857381

申请日：2017-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Chih-Chiang Chang ,  Wen-Chu Hsiao

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.

公开(公告)号：US10026662B2

公开(公告)日：2018-07-17

申请号：US14934517

申请日：2015-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsueh-Chang Sung ,  Chih-Chiang Chang ,  Kun-Mu Li

IPC: H01L21/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/04 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.

公开(公告)号：US09991364B2

公开(公告)日：2018-06-05

申请号：US15612137

申请日：2017-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/737 ,  H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L21/265 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

公开(公告)号：US20170271478A1

公开(公告)日：2017-09-21

申请号：US15612137

申请日：2017-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7378 ,  H01L29/7842 ,  H01L29/7847 ,  H01L29/7848

Abstract: A transistor device includes a gate structure disposed over a channel region of a semiconductor substrate. A source/drain recess is arranged in the semiconductor substrate alongside the gate structure. A doped silicon-germanium (SiGe) region is disposed within the source/drain recess and has a doping type which is opposite to that of the channel. An un-doped SiGe region is also disposed within the source/drain recess. The un-doped SiGe region underlies the doped SiGe region and comprises different germanium concentrations at different locations within the source/drain recess.

公开(公告)号：US09768178B2

公开(公告)日：2017-09-19

申请号：US14938311

申请日：2015-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7853

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure.

公开(公告)号：US20150349065A1

公开(公告)日：2015-12-03

申请号：US14288587

申请日：2014-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/36 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L27/092

Abstract: The present disclosure provides an integrated circuit device including n-channel and p-channel MOSFETs. The MOSFETs include epitaxial grown raised source/drain regions and epitaxial grown channel regions. An epitaxially grown diffusion barrier layer separates the epitaxial grown channel regions from underlying deep n-wells and p-wells. The epitaxial source/drain regions allow for a low thermal budget that in combination with the diffusion barrier layer allows the deep n-wells and p-wells to be heavily doped while preserving high purity in the channel layers.

Abstract translation: 本公开提供了包括n沟道和p沟道MOSFET的集成电路器件。 MOSFET包括外延生长的升高的源极/漏极区域和外延生长的沟道区域。 外延生长的扩散阻挡层将外延生长的沟道区域从下面的深n阱和p阱分离。 外延源极/漏极区域允许低热量预算，与扩散阻挡层组合允许深n阱和p阱重掺杂，同时在通道层中保持高纯度。