公开(公告)号：US12075607B2

公开(公告)日：2024-08-27

申请号：US18069765

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jing Lee ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Kun-Mu Li

IPC: H10B10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

CPC classification number: H10B10/12 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/7853 ,  H01L29/165

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

公开(公告)号：US12062720B2

公开(公告)日：2024-08-13

申请号：US18186244

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Hsueh-Chang Sung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

公开(公告)号：US20230352589A1

公开(公告)日：2023-11-02

申请号：US18346511

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Heng-Wen Ting ,  Yen-Ru Lee ,  Hsueh-Chang Sung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02129 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6681

Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium concentration that is smaller than the second germanium concentration.

公开(公告)号：US11610994B2

公开(公告)日：2023-03-21

申请号：US17199734

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Hsueh-Chang Sung

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

公开(公告)号：US20200343381A1

公开(公告)日：2020-10-29

申请号：US16925490

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

公开(公告)号：US10707328B2

公开(公告)日：2020-07-07

申请号：US15581778

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Kun-Mu Li

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/08 ,  H01L29/06

Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.

公开(公告)号：US09691898B2

公开(公告)日：2017-06-27

申请号：US14134302

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: C30B25/14 ,  H01L29/36 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

公开(公告)号：US20150179796A1

公开(公告)日：2015-06-25

申请号：US14134302

申请日：2013-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation.

Abstract translation: 本发明涉及具有应变源极/漏极区域的晶体管器件，其包括具有不连续锗浓度分布的应变诱发材料。 在一些实施例中，晶体管器件具有设置在半导体衬底上的栅极结构。 具有应变诱导材料的源极/漏极区域沿着栅极结构的侧面设置在半导体衬底中的源极/漏极凹部内。 应变诱导材料沿着从源极/漏极凹部的底表面延伸到源极/漏极凹部的顶表面的线具有不连续的锗浓度分布。 不连续的锗浓度分布提供改进的应变增强和位错传播。

公开(公告)号：US20240363753A1

公开(公告)日：2024-10-31

申请号：US18766828

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Hsueh-Chang Sung

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

公开(公告)号：US12112986B2

公开(公告)日：2024-10-08

申请号：US17382562

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Mu Li ,  Heng-Wen Ting ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chien-Wei Lee

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.