公开(公告)号：US20110241423A1

公开(公告)日：2011-10-06

申请号：US12752515

申请日：2010-04-01

申请人： Jeffrey Todd Bridges ,  Sanjay B. Patel

发明人： Jeffrey Todd Bridges ,  Sanjay B. Patel

IPC分类号： H02J1/00

CPC分类号： G06F1/305 ,  Y10T307/406

摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

摘要翻译： 公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。 在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。 当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。 当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。 以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

公开(公告)号：US20110140752A1

公开(公告)日：2011-06-16

申请号：US12637321

申请日：2009-12-14

申请人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

发明人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

摘要翻译： 公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。 在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。 时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。 反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。 输入信号可用于向功能电路提供时钟信号。

公开(公告)号：US20080174373A1

公开(公告)日：2008-07-24

申请号：US11624995

申请日：2007-01-19

申请人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

发明人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

IPC分类号： H03L7/099 ,  H03L7/08

CPC分类号： H03L7/189 ,  H03L2207/06

摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

摘要翻译： 公开了一种采用多个振荡器复合器的锁相环。 锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。 锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。