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公开(公告)号：US20090066376A1
公开(公告)日：2009-03-12
申请号：US12270731
申请日：2008-11-13
IPC分类号： H03K3/00
CPC分类号： H04L25/03885
摘要： A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.
摘要翻译： 具有降低的寄生电容的信令电路。 信令电路包括多个驱动器电路，每个驱动器电路各自具有耦合到第一输出节点的输出，以及多个选择电路，每个选择电路具有耦合到相应的一个驱动器电路的控制输入的输出。 每个选择电路包括用于接收相应选择信号的控制输入和用于接收多个数据信号的多个数据输入。 每个选择电路适于根据相应的选择信号选择要输出到对应的一个驱动器电路的控制输入的多个数据信号之一。
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公开(公告)号：US06982587B2
公开(公告)日：2006-01-03
申请号：US10261875
申请日：2002-10-01
IPC分类号： G06G7/12
CPC分类号： H04L25/03885
摘要： A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.
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公开(公告)号：US07412016B2
公开(公告)日：2008-08-12
申请号：US11428818
申请日：2006-07-05
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H04L7/0087 , H04L7/0334 , H04L7/0337
摘要： A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.
摘要翻译： 用于调整时钟信号相位的电路。 第一采样电路响应于时钟信号的转变而生成数据样本序列，根据输入信号是否超过第一阈值，每个数据样本具有第一状态或第二状态。 第二采样电路根据输入信号是否超过第二阈值，响应于时钟信号的转换之一产生误差采样，该误差采样具有第一状态或第二状态。 如果数据样本序列与预定模式匹配并且至少部分地基于该误差样本是否具有第一状态或第二状态，则相位调整电路调整时钟信号的相位。
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公开(公告)号：US07176721B2
公开(公告)日：2007-02-13
申请号：US11022291
申请日：2004-12-24
申请人： Andrew Ho , Vladimir M. Stojanovic
发明人： Andrew Ho , Vladimir M. Stojanovic
IPC分类号： H03K17/16
CPC分类号： H04L25/03057 , H04L25/028 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L25/4906
摘要： In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
摘要翻译： 在数据进位接收机中，采样电路产生输入信号的多个采样，并将多个样本依次存储在第一存储缓冲器中。 响应于每个断言第一控制信号，多个样本的第一子集从第一存储缓冲器传送到解码器电路，并且多个样本的第二子集从第一存储缓冲器传送到抽头权重 响应于每个断言第二控制信号的更新电路，所述第二选通信号相对于所述第一控制信号被异步地断言。 抽头加权更新电路至少部分地基于多个样本的第二子集生成多个更新抽头加权。
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公开(公告)号：US07348811B2
公开(公告)日：2008-03-25
申请号：US11251139
申请日：2005-10-14
IPC分类号： H03K3/10
CPC分类号： H04L25/03885
摘要： A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.
摘要翻译： 具有降低的寄生电容的信令电路。 信令电路包括多个驱动器电路，每个驱动器电路各自具有耦合到第一输出节点的输出，以及多个选择电路，每个选择电路具有耦合到相应的一个驱动器电路的控制输入的输出。 每个选择电路包括用于接收相应选择信号的控制输入和用于接收多个数据信号的多个数据输入。 每个选择电路适于根据相应的选择信号选择要输出到对应的一个驱动器电路的控制输入的多个数据信号之一。
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公开(公告)号：US07092472B2
公开(公告)日：2006-08-15
申请号：US10867153
申请日：2004-06-14
IPC分类号： H04L25/38
CPC分类号： H04L7/0331 , H04L7/0087 , H04L7/0334 , H04L7/0337
摘要： A circuit for adjusting the phase of a clock signal. A first sampling circuit generates a sequence of data samples in response to transitions of the clock signal, each of the data samples having either a first state or a second state according to whether an incoming signal exceeds a first threshold. An second sampling circuit generates an error sample in response to one of the transitions of the clock signal, the error sample having either the first state or the second state according to whether the incoming signal exceeds a second threshold. A phase adjust circuit adjusts the phase of the clock signal if the sequence of data samples matches a predetermined pattern and based, at least in part, on whether the error sample has the first state or the second state.
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