Abstract:
A content search circuit for determining whether an input string matches one or more of a plurality of regular expressions, the content search circuit including an instruction memory for storing a plurality of microprograms, each microprogram embodying a corresponding one of the regular expressions, a control circuit having an input to receive the input string, and having a number of outputs, and a plurality of search engines, each having a first input coupled to a corresponding output of the control circuit and having a second input coupled to the instruction memory, wherein each search engine is selectable to execute any of the microprograms stored in the instruction memory to search the input string for any of the regular expressions embodied in the microprograms.
Abstract:
A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In various embodiments, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.
Abstract:
A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one compare data value can driven on two of the value lines, while the other two value lines can be forced to a potential unrelated to a compare data value allowing for dynamic configuration between binary and ternary modes of operation.
Abstract:
A method, apparatus, and storage medium product are provided for forming a forwarding database, and for using the formed database to more efficiently and quickly route packets of data across a computer network. The forwarding database is arranged into multiple sub-databases. Each sub-database is pointed to by a pointer within a pointer table. When performing a longest-match search of incoming addresses, a longest prefix matching algorithm can be used to find the longest match among specialized “spear prefixes” stored in the pointer table. After the longest spear prefixes are found, the pointer table will direct the next search within a sub-database pointed to by that spear prefix. Another longest-match search can be performed for database prefixes (or simply “prefixes”) within the sub-database selected by the pointer. Only the sub-database of interest will, therefore, be searched and all other sub-databases are not accessed. Using a precursor pointer and a sub-database of optimally bounded size and number ensures power consumption be confined only to the sub-database being accessed, and that higher speed lookup operations can be achieved since only the sub-database of interest is being searched.
Abstract:
A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the memory, and the plurality of address values are queued within the first-in-first-out storage circuit to enable the address values to be read in succession by an external device.
Abstract:
A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a bit indicating a traffic type for the packet, and compare logic coupled to the CAM device and configured to determine which of the departure times stored in the CAM device is the earliest.
Abstract:
A content search system for determining whether a plurality of input strings each belonging to any one of a number of different process flows matches one or more of a plurality of regular expressions, including a search circuit for searching the input strings for the regular expressions and a data management unit including a control circuit having an input to receive the plurality of input strings, wherein each input string has an associated flow identification (ID) value, a packet queue having a number of storage locations for storing the input strings, and a flow engine that forwards a selected input string from the packet queue to the search circuit.
Abstract:
A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.
Abstract:
A hierarchical programmable-priority content addressable memory (CAM) system including first, second and third CAM devices. The first CAM device has a first priority number output and a first enable input. The second CAM device has a priority number input and an enable output coupled to the priority number output and the first enable input, respectively, of the first CAM device. The second CAM device also has a priority number output and an enable input. The third CAM device has a priority number input and an enable output coupled to the priority number output and the enable input, respectively, of the second CAM device.
Abstract:
A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first data line pairs, each second data line pair having a first and second constituent data lines that cross one another at a point along their lengths.