公开(公告)号：US12063162B2

公开(公告)日：2024-08-13

申请号：US16718964

申请日：2019-12-18

Applicant: DOLBY LABORATORIES LICENSING CORPORATION

Inventor： Xuejing Sun ,  Zhiwei Shuang

IPC: H04L47/56 ,  H04L1/20 ,  H04L43/087 ,  H04L47/283 ,  H04L65/80 ,  H04W16/18 ,  H04W24/02 ,  H04W28/02 ,  H04W48/18 ,  H04W72/04 ,  H04W72/12 ,  B60L1/00 ,  B60L53/14 ,  B60L55/00 ,  H02M1/00 ,  H02M1/14 ,  H02M1/42 ,  H02M5/458 ,  H02M7/48 ,  H02M7/79 ,  H04L47/2416

CPC classification number: H04L47/56 ,  H04L1/205 ,  H04L43/087 ,  H04L47/283 ,  H04L65/80 ,  H04W16/18 ,  H04W24/02 ,  H04W28/02 ,  H04W48/18 ,  H04W72/04 ,  H04W72/12 ,  B60L1/00 ,  B60L53/14 ,  B60L55/00 ,  H02M1/007 ,  H02M1/14 ,  H02M1/42 ,  H02M5/458 ,  H02M7/4807 ,  H02M7/79 ,  H04L47/2416 ,  Y02B70/10

Abstract: Apparatus and methods for controlling a jitter buffer are described. In one embodiment, the apparatus for controlling a jitter buffer includes an inter-talkspurt delay jitter estimator for estimating an offset value of the delay of a first frame in the current talkspurt with respect to the delay of a latest anchor frame in a previous talkspurt, and a jitter buffer controller for adjusting a length of the jitter buffer based on a long term length of the jitter buffer for each frame and the offset value.

公开(公告)号：US11973674B2

公开(公告)日：2024-04-30

申请号：US16990458

申请日：2020-08-11

Applicant: Nokia Solutions and Networks Oy

Inventor： Andrea Enrici ,  Bogdan Uscumlic ,  Julien Lallet

IPC: H04L43/0852 ,  G06F16/901 ,  G06F30/34 ,  H04L47/56 ,  H04L47/74 ,  H04L47/80 ,  H04L47/83

CPC classification number: H04L43/0852 ,  G06F16/9017 ,  G06F30/34 ,  H04L47/56 ,  H04L47/745 ,  H04L47/801 ,  H04L47/805 ,  H04L47/83

Abstract: A method for allocating resources of a field-programmable gate array (FPGA), the method comprising: deterministically estimating a maximum latency for executing a network service at the FPGA; determining that the maximum latency is less than a threshold latency value associated with the network service; outputting an acknowledgement indicating that the maximum latency is less than or equal to the threshold latency value; receiving confirmation that the FPGA has been selected to execute the network service within a threshold time period; and deterministically scheduling the resources of the FPGA for executing the network service in response to receiving the confirmation within the threshold time period.

公开(公告)号：US11902167B2

公开(公告)日：2024-02-13

申请号：US17624464

申请日：2019-07-04

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Tatsuya Fukui ,  Katsuya Minami ,  Yuki Sakaue ,  Hiroyuki Furukawa

IPC: H04L47/215 ,  H04L47/52 ,  H04L47/56 ,  H04L47/50

CPC classification number: H04L47/215 ,  H04L47/528 ,  H04L47/56 ,  H04L47/58

Abstract: An object is to provide a communication apparatus, a communication method, and a program capable of avoiding an increase in network load when input traffic continues to be large and a communication delay when input traffic is very small. A communication apparatus according to the present invention prepares three token buckets and can transfer, discard, or hold a packet in accordance with the amount of tokens in each token bucket. This enables the communication apparatus to operate so as not to exceed a set maximum bandwidth when large traffic is received for the delay guarantee shaping. Further, When the maximum bandwidth is exceeded, the communication apparatus can select whether to discard a packet to prioritize a delay guarantee or to hold a packet to prioritize no loss of packets. Furthermore, the communication apparatus can immediately transmit a packet without increasing a communication delay when input traffic is very small.

公开(公告)号：US20230379264A1

公开(公告)日：2023-11-23

申请号：US18315001

申请日：2023-05-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Yeoncheol RYOO ,  Taesik CHEUNG

IPC: H04L47/56 ,  H04L45/302 ,  H04L43/0852

CPC classification number: H04L47/56 ,  H04L45/302 ,  H04L43/0852

Abstract: The present disclosure relates generally to a communication system, and more particularly, to a method for time-deterministic packet forwarding that guarantees a maximum and minimum latency requirement of a service, the method including: receiving latency information of links and nodes on a path, and buffer resource information of the nodes; calculating, on the basis of the buffer resource information of the last node, local latency budgets that the other nodes need to guarantee; performing control so that the nodes transmit a packet on the basis of the local latency budgets; and finally guaranteeing, by the last node, a residual latency budget remaining after the nodes transmit the packet within the local latency budgets.

公开(公告)号：US11785113B2

公开(公告)日：2023-10-10

申请号：US16661559

申请日：2019-10-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yujie Chen

IPC: H04L67/568 ,  H04L47/2408 ,  H04L47/56 ,  H04L45/50 ,  H04L67/60 ,  H04L47/52 ,  H04L67/62

CPC classification number: H04L67/568 ,  H04L45/50 ,  H04L45/502 ,  H04L47/2408 ,  H04L47/52 ,  H04L47/56 ,  H04L67/60 ,  H04L67/62

Abstract: This application discloses a client service transmission method and apparatus. The method may include: receiving a client service, where the client service includes a plurality of data blocks, the client service is corresponding to a counter, and the counter is used to control an output rate of the client service; and sending the plurality of data blocks in a plurality of sending periods, where when a count value of the counter reaches a preset threshold in each sending period, at least one data block of the plurality of data blocks is sent. This technology may be applied to a scenario in which a transmission node transmits a client service.

公开(公告)号：US20230283565A1

公开(公告)日：2023-09-07

申请号：US17653801

申请日：2022-03-07

Applicant: NXP B.V.

Inventor： Bernard Francois St-Denis ,  Sathish Vallipuram

IPC: H04L47/56 ,  H04L49/25

CPC classification number: H04L47/56 ,  H04L49/252 ,  H04L49/251

Abstract: Cut-through frame transfer or store-and-forward frame transfer of a frame in an network switch is disclosed. A frame is received from an input port of the switch. A time period in a cycle time when the frame is received and a stream identification of the frame is determined. One of the cut-through frame transfer and the store-and-forward frame transfer of the frame is performed based on the time period in the cycle time when the frame was received and the stream identification.

公开(公告)号：US11736408B2

公开(公告)日：2023-08-22

申请号：US17423484

申请日：2020-07-15

Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS

Inventor： Min Wei ,  XueQin Xiang ,  Ping Wang ,  XianChun Yan

IPC: H04L47/52 ,  H04L41/0896 ,  H04L45/00 ,  H04L47/24 ,  H04L47/56

CPC classification number: H04L47/522 ,  H04L41/0896 ,  H04L45/14 ,  H04L47/2458 ,  H04L47/56

Abstract: A scheduling method applied in an industrial heterogeneous network in which a TSN and a non-TSN are interconnected is provided. The TSSDN controller classifies data flows according to the delay requirements, and calculates the scheduling priorities of the data flows in the industrial heterogeneous network. The TSSDN controller adopts an improved CSPF algorithm to determine a shortest path in the heterogeneous network, and marks the scheduling priorities of the data flows which are transmitted from the subnet of the heterogeneous network and arrive at the switch for the first time. Flow table matching is performed at the SDN switch. In a case of performing flow table matching successfully, the counter is updated and the instruction included in the flow table is executed. In a case of performing flow table matching unsuccessfully, a PacketIn message is transmitted to the TSSDN controller, and the TSSDN controller performs analysis and makes a decision.

公开(公告)号：US11677677B2

公开(公告)日：2023-06-13

申请号：US16981556

申请日：2019-06-25

Applicant: BAE Systems Information And Electronic Systems Integration Inc.

Inventor： Matthew J. Sherman ,  Haley H. Kim ,  Joseph E. Stepien ,  Alan E. Trojan ,  Matthew Rasa ,  Nicholas C. Sherman

IPC: H04W4/00 ,  H04L47/72 ,  H04L41/5003 ,  H04L7/00 ,  H04L47/56 ,  H04W48/16 ,  H04W72/0446

CPC classification number: H04L47/72 ,  H04L7/0008 ,  H04L41/5003 ,  H04L47/56 ,  H04W48/16 ,  H04W72/0446

Abstract: A set of methods for discovery of nodes where at least some of the nodes use directional antennas is presented. The methods consist primarily of partitioning the search space into tiers based on elevation angles and adjusting parameters used to construct tiling patterns and slots for discovery messaging, and search methods patterns. The methods further include partitioning into subslots as well as characterization of HAIL slots and rendezvous slots. The HAIL slots and rendezvous slots are allocated within a search schedule and synched across multiple platforms for greater efficiency of communication.

公开(公告)号：US20230171201A1

公开(公告)日：2023-06-01

申请号：US18159875

申请日：2023-01-26

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shoushou REN ,  Bingyang LIU ,  Rui MENG ,  Chuang WANG ,  Jean-Yves LEBOUDEC ,  Ehsan MOHANMMADPOUR ,  Alaeddine ELFAWAL

IPC: H04L47/6275 ,  H04L47/56 ,  H04L49/00

CPC classification number: H04L47/6275 ,  H04L47/56 ,  H04L49/3018 ,  H04L49/3027

Abstract: Embodiments of this application provide a method for sending a data packet. The method includes: A second network device may determine a remaining processing time of a data packet on a first network device based on a predefined first delay. When the remaining processing time is greater than 0, a moment at which the data packet enters a queue on the second network device serves as a start moment, and after a period of time, the remaining processing time ends at a second reference moment corresponding to the data packet. The remaining processing time is consumed on the second network device.

公开(公告)号：US20190036832A1

公开(公告)日：2019-01-31

申请号：US15663084

申请日：2017-07-28

Applicant: Cisco Technology, Inc.

Inventor： John J. Williams, JR. ,  Naader Hasani ,  Mohammed Ismael Tatar ,  David Delano Ward

IPC: H04L12/801 ,  H04L12/861 ,  H04L12/875

CPC classification number: H04L47/34 ,  H04L47/56 ,  H04L49/25 ,  H04L49/9057

Abstract: In one embodiment, for each distribution period of time, each packet flow is assigned to a path through a packet switching device (e.g., switch fabric) with all packets of the packet flow being sent in order over the assigned path. For a next distribution period, different paths are assigned for these packet flows, with all packets being sent in order over the new corresponding selected path. In one embodiment, these paths are switched often enough to prevent congestion, yet infrequent enough so as to minimize resources for reordering. In one embodiment, the reordering is done at the egress and only for predefined high bandwidth flows (e.g., elephant flows). A distribution period indication is typically associated with each packet to identify its corresponding distribution period. In one embodiment, each routing and egress switching stage in a switching fabric performs reordering.