公开(公告)号：US20170228281A1

公开(公告)日：2017-08-10

申请号：US15514578

申请日：2015-09-28

申请人： FTS COMPUTERTECHNIK GMBH

发明人： Stefan POLEDNA ,  Hermann KOPETZ

IPC分类号： G06F11/07 ,  G06F11/20

CPC分类号： G06F11/0796 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/185 ,  G06F2201/805

摘要： The invention relates to a time-controlled distribution unit (30, 31) for the distribution of messages in a distributed computer system for safety-critical applications. Said distribution unit is designed as a self-testing functional unit and comprises input channels (201 . . . 222) for receiving time-controlled periodic input messages from node computers (20, 21, 22) upstream in the data flow, and output channels (301 . . . 333) for transmitting time-controlled periodic output messages to the node computers (50, 51, 52) downstream in the data flow, a computer (40) being provided in the distribution unit and being designed to analyze, by means of a “simple” software, useful information contained in the input messages, and to decide whether output messages are output and, if so, which useful information is contained in the output messages.

公开(公告)号：US20160034368A1

公开(公告)日：2016-02-04

申请号：US14801825

申请日：2015-07-17

申请人： Renesas Electronics Corporation

发明人： Osamu Nishii ,  Kiwamu Takada

IPC分类号： G06F11/20

CPC分类号： G06F11/1637 ,  G06F11/1004 ,  G06F11/1405 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1695

摘要： Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.

摘要翻译： 常规的半导体器件的问题在于，在执行锁定步骤操作的CPU核心之一的故障的情况下不能继续操作，结果不能提高可靠性。 根据本发明的半导体器件包括：计算单元，包括执行锁定步骤操作的第一CPU核心和第二CPU核心，其中第一CPU核心11和第二CPU核心12分别诊断内部逻辑电路的故障，以及 基于诊断结果，顺序控制电路将计算单元中输出数据的CPU核心切换到共享资源。

公开(公告)号：US08959392B2

公开(公告)日：2015-02-17

申请号：US13636070

申请日：2011-03-18

申请人： Adrian Traskov ,  Thorsten Ehrenberg ,  Lukusa Didier Kabulepa ,  Felix Wolf

发明人： Adrian Traskov ,  Thorsten Ehrenberg ,  Lukusa Didier Kabulepa ,  Felix Wolf

IPC分类号： G06F11/00 ,  G06F11/16

CPC分类号： G06F11/165 ,  G06F11/1641 ,  G06F11/1645

摘要： A redundant two-processor controller having a first processor (1) and a second processor (1) for the synchronous execution of a control program. The controller having at least a first multiplexer (70, 91) for optionally connecting at least a first peripheral unit (72, 95) to be actuated to one of the two processors (1, 2), and at least a first Comparison unit (70, 91) for monitoring the synchronization state of the two processors (1, 2) and for detecting a synchronization error. A restoration control unit (44) is designed to monitor the execution of at least one test program by the two processors (1, 2) after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer (70, 91).

摘要翻译： 一种具有用于控制程序的同步执行的第一处理器（1）和第二处理器（1）的冗余双处理器控制器。 所述控制器具有至少第一多路复用器（70,91），用于可选地连接至少第一外围单元（72,95）以被致动到所述两个处理器（1,2）中的一个，以及至少第一比较单元（ 用于监视两个处理器（1,2）的同步状态并检测同步错误。 恢复控制单元（44）被设计成在发生同步错误之后监视由两个处理器（1,2）执行的至少一个测试程序的执行并评估测试结果，并且被设计为至少配置 第一多路复用器（70,91）。

公开(公告)号：US08935569B2

公开(公告)日：2015-01-13

申请号：US13636091

申请日：2011-03-18

申请人： Lukusa Didier Kabulepa ,  Thorsten Ehrenberg ,  Daniel Baumeister

发明人： Lukusa Didier Kabulepa ,  Thorsten Ehrenberg ,  Daniel Baumeister

IPC分类号： G06F11/00 ,  G06F11/16 ,  G06F11/20

CPC分类号： G06F11/1641 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043

摘要： A control computer system comprising at least two modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit (20, 21, 91, 92, 1011, 1012) for monitoring the synchronization state of the at least two redundant modules (1, 2, 1001, 1002, 1003, 1004, 1021, 1071) and for detecting a synchronization error at least one peripheral unit (95, 96, 1022, 1030, 1031, . . . , 1038). At least one switching matrix (21, 1013, 1063) which is set up to allow or block access to the at least two redundant modules or access to the peripheral unit (95, 96, 1022, 1030, 1031, . . . , 1038) by the at least two redundant modules, and an error-handling unit (44, 1080) which is set up to receive signals from the at least one comparison unit (20, 21, 91, 92, 1011, 1012) and to drive the at least one switching matrix (1013, 1063) in order to completely or selectively prevent access to the at least two redundant modules or access to the peripheral unit by the at least two redundant modules.

摘要翻译： 一种控制计算机系统，包括被设计为相对于彼此冗余的至少两个模块（1,2,1001,1002,1003,1004,1021,1071）。 所述控制计算机系统具有至少一个比较单元（20,21,91,92,1011,1012），用于监视所述至少两个冗余模块（1,2,1001,1002,1003,1004,1012,1012,1012,1012） 1071），并且用于检测至少一个外围单元（95,96,1022,1030,1031，...，1038）的同步错误。 至少一个开关矩阵（21,1013,1063）被设置为允许或阻止访问至少两个冗余模块或访问外围单元（95,96,1022,1030,1031,10 ... 1038） ），以及错误处理单元（44，1080），其被设置为从所述至少一个比较单元（20,21,91,92,1011,1012）接收信号并驱动 所述至少一个交换矩阵（1013,1063），以完全或选择性地防止对所述至少两个冗余模块的访问或由所述至少两个冗余模块访问所述外围单元。

公开(公告)号：US08799706B2

公开(公告)日：2014-08-05

申请号：US11042985

申请日：2005-01-25

申请人： William F. Bruckert ,  David J. Garcia ,  Thomas A. Heynemann ,  James S. Klecka ,  Jeffrey A. Sprouse

发明人： William F. Bruckert ,  David J. Garcia ,  Thomas A. Heynemann ,  James S. Klecka ,  Jeffrey A. Sprouse

IPC分类号： G06F11/00

CPC分类号： G06F11/1687 ,  G06F11/1645

摘要： A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

摘要翻译： 一种在处理器之间交换信息的方法和系统。 说明性实施例中的至少一些可以是一种方法，包括通过将（第一处理器）第一数据写入逻辑设备，然后由第一处理器继续处理用户程序，在多个处理器之间交换信息，由（第 第二处理器）到逻辑设备的第二数据，然后由第二处理器继续处理用户程序，并且在所有处理器具有第一处理器和第二处理器之后，通过逻辑器件将第一和第二数据写入第一和第二处理器 将其各自的基准写入逻辑设备。

公开(公告)号：US08499193B2

公开(公告)日：2013-07-30

申请号：US12847687

申请日：2010-07-30

申请人： Nicholas Wilt ,  Scott Gray

发明人： Nicholas Wilt ,  Scott Gray

IPC分类号： G06F11/00

CPC分类号： G06F11/1645 ,  G06F11/1637

摘要： A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

摘要翻译： 提供了一种自检网络，包括被配置为执行演奏功能的第一命令处理器和被配置为执行与第一命令处理器耦合的演奏功能的第二命令处理器。 自检网络还包括被配置为执行耦合到第一命令处理器的监视功能的第一监视器处理器和被配置为执行耦合到第二命令处理器的监视功能的第二监视器处理器。 第一和第二命令处理器比较输出，第一和第二监视器处理器比较输出，并且第一监视器处理器确定第一命令处理器的输出是否超过第一选择的限制。

公开(公告)号：US08499189B2

公开(公告)日：2013-07-30

申请号：US13708931

申请日：2012-12-08

申请人： International Business Machines Corporation

发明人： Rajaram B. Krishnamurthy ,  Carl J. Parris ,  Donald W. Schmidt ,  Benjamin P. Segal

IPC分类号： G06F11/00

CPC分类号： G06F9/50 ,  G06F11/008 ,  G06F11/1645 ,  G06F11/188

摘要： A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized.

摘要翻译： 一种用于在计算机系统中维持可靠性的方法，系统和计算机程序产品。 在示例实施例中，该方法包括由第一组处理器执行第一数据计算，第一组处理器具有第一计算机处理器架构。 该方法通过由耦合到第一组处理器的第二处理器执行第二数据计算而继续，第二处理器具有第二计算机处理器架构，第一计算机处理器架构不同于第二计算机处理器架构。 最后，该方法包括在第一组处理器和第二处理器运行时基于至少一个度量来动态分配第一组处理器和第二处理器的计算资源，使得第一数据计算的精度和处理速度 并且第二数据计算被优化。

公开(公告)号：US08386843B2

公开(公告)日：2013-02-26

申请号：US12223843

申请日：2006-12-15

申请人： Darren Stewart Learmonth

发明人： Darren Stewart Learmonth

IPC分类号： G06F11/00

CPC分类号： G06F11/1645

摘要： A high speed data processing system is described comprising first and second data processing modules and first and second data checking modules. The first and second data processing modules are each arranged to perform substantially the same processing steps on data received at said data input, with each providing an output. The first and second checking modules are arranged to compare the outputs of said first and second data processing modules and to output an error signal indicative of whether or not said first and second data processing modules have performed substantially the same processing steps. The first and second checking modules are located on physically separate devices. In some arrangements a third checking module is provided, which checking module may be physically separated from each of said first and second checking modules.

摘要翻译： 描述了包括第一和第二数据处理模块以及第一和第二数据检查模块的高速数据处理系统。 第一和第二数据处理模块分别被布置为对在所述数据输入端接收到的数据执行基本相同的处理步骤，每个提供输出。 第一和第二检查模块被布置成比较所述第一和第二数据处理模块的输出，并输出指示所述第一和第二数据处理模块是否执行了基本上相同的处理步骤的错误信号。 第一和第二检查模块位于物理上分离的设备上。 在一些布置中，提供了第三检查模块，该检查模块可以与所述第一和第二检查模块中的每一个物理分离。

公开(公告)号：US20120089867A1

公开(公告)日：2012-04-12

申请号：US13251037

申请日：2011-09-30

申请人： Eric J. Bartlett ,  Matthew J. Fairhurst ,  William J. Scales

发明人： Eric J. Bartlett ,  Matthew J. Fairhurst ,  William J. Scales

IPC分类号： G06F11/16

CPC分类号： G06F11/2094 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0689 ,  G06F11/1088 ,  G06F11/1645 ,  G06F11/2092 ,  G06F2201/805

摘要： In one embodiment, a system includes a storage subsystem having an array of storage devices; a receiving component for receiving an error message; a determining component for determining that the error message indicates that a storage device has failed; a collecting component for collecting an array record having storage device characteristics of the failed storage device; a collating component for collating a candidate record having a plurality of candidate entries; a comparing component for comparing storage device characteristics of the failed storage device of the array record with the storage device characteristics of each of the candidate entries; and an identifying component for identifying a first candidate storage device having storage device characteristics that match the storage device characteristics of the failed storage device or a second candidate storage device having storage device characteristics most similar to the storage device characteristics of the failed storage device.

摘要翻译： 在一个实施例中，系统包括具有存储设备阵列的存储子系统; 用于接收错误消息的接收组件; 用于确定所述错误消息指示存储设备已经失败的确定组件; 用于收集具有所述故障存储设备的存储设备特性的阵列记录的收集组件; 用于对准具有多个候选条目的候选记录的对照组件; 用于比较阵列记录的故障存储装置的存储装置特性与每个候选条目的存储装置特性的比较部件; 以及识别组件，用于识别具有与故障存储设备的存储设备特性匹配的存储设备特性的第一候选存储设备或具有与故障存储设备的存储设备特性最相似的存储设备特性的第二候选存储设备。

公开(公告)号：US20120066545A1

公开(公告)日：2012-03-15

申请号：US13229956

申请日：2011-09-12

申请人： SHINJI ABE

发明人： SHINJI ABE

IPC分类号： G06F11/00

CPC分类号： G06F11/2028 ,  G06F11/1645 ,  G06F11/1654 ,  G06F11/2038

摘要： A fault-tolerant system including a plurality of modules each further including a CPU subsystem, a fault-tolerant control unit, and an I/O subsystem, wherein the fault-tolerant control unit includes a master FT control LSI chip and at least one slave FT control LSI chip. One module is placed in an active state whilst the other module is placed in a standby state, so that I/O requests made by CPU subsystems of these modules are selectively delivered to I/O subsystems based on the master/slave relationship. Upon receiving fault information representing a failed subsystem which is either the CPU subsystem or the I/O subsystem found in the module, the master FT control LSI chip sends a command for controlling isolation of the failed subsystem to the slave FT control LSI chip, so that the slave FT control LSI chip controls isolation of the failed subsystem based on the command.

摘要翻译： 一种容错系统，包括多个模块，每个模块还包括CPU子系统，容错控制单元和I / O子系统，其中所述容错控制单元包括主FT控制LSI芯片和至少一个从机 FT控制LSI芯片。 一个模块处于活动状态，而另一个模块处于待机状态，这样，这些模块的CPU子系统所产生的I / O请求将根据主/从关系选择性地传送到I / O子系统。 主机FT控制LSI芯片接收到代表模块中发现的CPU子系统或I / O子系统的故障子系统的故障信息时，发送用于控制故障子系统与从FT控制LSI芯片隔离的命令，因此 从属FT控制LSI芯片根据命令控制故障子系统的隔离。