公开(公告)号：US5636358A

公开(公告)日：1997-06-03

申请号：US217126

申请日：1994-03-24

申请人： William A. Brant ,  Gerald L. Hohenstein

发明人： William A. Brant ,  Gerald L. Hohenstein

IPC分类号： G06F3/06 ,  G06F13/40 ,  G06F12/08

CPC分类号： G06F3/0601 ,  G06F13/4059 ,  G06F2003/0691

摘要： A computer storage system having a dual port buffer memory for improved performance. The invention comprises a computer storage subsystem that includes a dual port buffer memory that effectively provides two internal data busses for the storage subsystem: one bus for data transfers between the dual port buffer memory and the storage units, and a second bus for data transfers between the dual port buffer memory and a CPU. The throughput of the storage subsystem is roughly equivalent to the bandwidth of the slower of the two busses. In alternative configurations, the invention may use a plurality of dual port buffer memories in parallel to increase the effective throughput of the storage subsystem, and better match the bandwidth of the two busses.

摘要翻译： 一种具有用于改善性能的双端口缓冲存储器的计算机存储系统。 本发明包括计算机存储子系统，其包括有效地为存储子系统提供两个内部数据总线的双端口缓冲存储器：用于在双端口缓冲存储器和存储单元之间进行数据传输的一个总线，以及用于在第二总线之间进行数据传输的第二总线 双端口缓冲存储器和一个CPU。 存储子系统的吞吐量大致相当于两台总线较慢的带宽。 在替代配置中，本发明可以并行地使用多个双端口缓冲存储器来增加存储子系统的有效吞吐量，并且更好地匹配两个总线的带宽。

公开(公告)号：US5341479A

公开(公告)日：1994-08-23

申请号：US778301

申请日：1991-10-16

申请人： Robert E. Dean ,  Steven C. Cacka ,  Douglas P. Schaefer ,  Hossein F. Sevvom ,  Robert A. Brumnet

发明人： Robert E. Dean ,  Steven C. Cacka ,  Douglas P. Schaefer ,  Hossein F. Sevvom ,  Robert A. Brumnet

IPC分类号： G06F3/06 ,  G11B19/02 ,  G11B20/10 ,  G11B20/12 ,  G11B27/30 ,  G06F13/00

CPC分类号： G06F3/0601 ,  G11B19/02 ,  G11B20/10 ,  G11B20/12 ,  G11B27/3027 ,  G06F2003/0691 ,  G11B2020/10916

摘要： The address mark triggered read/write head buffer provides a buffer memory for each read/write head in the rotating media data storage system that stores the entire track of data that includes the requested data record. Thus, the address mark triggered read/write head buffer retrieves the requested data record independent of the control module so that a seek request from the processor can be handled as soon as the beginning of the next data record stored on the track is positioned below the associated read/write head. The entire track is thereby staged faster on the average than the time to retrieve the requested data record. The address mark triggered read/write head buffer includes an address mark detection circuit to identify the beginning of the data field in each data record. The address mark is a predetermined data pattern of n bits that is written on the track a predetermined distance in advance of the data field of the data record. The address mark detection circuit compares the n data bits most recently read from the track with this predetermined data pattern of n bits as stored in memory. Once a match is detected, the buffer is enabled to store the next data record written on the track and all subsequent data records on the track.

摘要翻译： 地址标记触发的读/写头缓冲器为旋转介质数据存储系统中的每个读/写头提供缓冲存储器，其存储包括所请求的数据记录的整个数据轨迹。 因此，地址标记触发的读/写头缓冲器独立于控制模块检索所请求的数据记录，使得一旦存储在轨道上的下一个数据记录的开始位于 相关的读/写头。 因此，整个轨道的平均时间比检索所请求的数据记录的时间更快。 地址标记触发的读/写头缓冲器包括一个地址标记检测电路，以识别每个数据记录中数据字段的开始。 地址标记是在数据记录的数据字段之前预定距离上写入轨道的n位的预定数据模式。 地址标记检测电路将最近从磁道读出的n个数据位与存储在存储器中的n位的这种预定数据模式进行比较。 一旦检测到匹配，缓冲区就可以存储写在轨道上的下一个数据记录和轨道上的所有后续数据记录。

公开(公告)号：US5329622A

公开(公告)日：1994-07-12

申请号：US780998

申请日：1991-10-23

申请人： Jay S. Belsan ,  Charles A. Milligan

发明人： Jay S. Belsan ,  Charles A. Milligan

IPC分类号： G06F3/06 ,  G06F13/14

CPC分类号： G06F3/0601 ,  G06F2003/0691

摘要： The multiple step data read apparatus provides a buffer memory (108-0) for each read/write head (110-0) in the rotating media (111-0) data storage system that can store up to the entire track (400) of data that includes the requested data (Sectors 2-6). The data is fragmented such that the data transferred into the read/write head buffer first is transmitted to the control unit first whether or not that data is at the beginning of the data requested by the control unit. The data is further fragmented such that critical portions of the data are available to the control unit to satisfy the host request as soon as the data is read from the device. This fragmenting results in the data becoming available to the control unit in the minimum time possible and the performance of the subsystem being the maximum possible. In addition each data fragment transfer to the control unit (104) is initiated a predetermined time before the end of the fragment of data such that the read/write head (110-0) reaches the end of the fragment the same time that the last sector of the fragment is transmitted to the control unit (104).

摘要翻译： 多步数据读取装置为旋转介质（111-0）数据存储系统中的每个读/写头（110-0）提供缓冲存储器（108-0），其可以存储直到整个轨道（400）的 数据包含所请求的数据（扇区2-6）。 数据被分段，使得首先将传送到读/写头缓冲器的数据首先发送到控制单元，无论该数据是否处于由控制单元请求的数据的开头。 数据进一步分段，使得数据的关键部分一旦从设备读取数据就可用于控制单元以满足主机请求。 这种碎片导致数据在最短时间内变得可用于控制单元，并且子系统的性能是最大可能的。 此外，每个数据片段传送到控制单元（104）在数据片段结束之前的预定时间开始，使得读/写头（110-0）到达片段的末端，同时最后 片段的扇区被发送到控制单元（104）。

公开(公告)号：US5274764A

公开(公告)日：1993-12-28

申请号：US668860

申请日：1991-03-13

申请人： Dae Y. Kim

发明人： Dae Y. Kim

IPC分类号： G11B7/08 ,  G06F3/06 ,  G11B20/10 ,  G06F5/06

CPC分类号： G06F3/0601 ,  G11B20/10 ,  G06F2003/0691 ,  G06F2003/0692 ,  G11B2020/10805

摘要： A continuous data input control system for an optical disk comprising an optical disk digital signal processor for outputting serial data, beat clock signal and left/right clock signal, an optical disk ROM decoder for decoding and transmitting the data from the processor, a microprocessor for controlling the whole system, and a data input controller for controlling the output of the digital signal processor. The data input controller includes a clock generator, a counter, a first control signal generator, an AND gate, a stop point detector for shifting the serial data of the digital signal processing unit by synchronization with the clock pulse signal of an AND gate, for latching the data when the buffer RAM is in the overflow state in response to the output level of the control signal generating unit, and for detecting the data of the stop point by comparing the latched data with the data being presently inputted, when the overflow of the buffer RAM is released. It also includes a second control signal generator, and a switching unit.By these arrangements, digital audio data on the optical disk can be reinputted from the data input stop point after the data input operation is stopped due to a buffer overflow.

摘要翻译： 一种用于光盘的连续数据输入控制系统，包括用于输出串行数据，差拍时钟信号和左/右时钟信号的光盘数字信号处理器，用于从处理器解码和发送数据的光盘ROM解码器，用于 控制整个系统，以及用于控制数字信号处理器的输出的数据输入控制器。 数据输入控制器包括时钟发生器，计数器，第一控制信号发生器，与门，用于通过与门的时钟脉冲信号同步地移位数字信号处理单元的串行数据的停止点检测器，用于 当缓冲器RAM响应于控制信号产生单元的输出电平处于溢出状态时，锁存数据，并且通过将锁存数据与当前输入的数据进行比较来检测停止点的数据，当溢出时 释放缓冲RAM。 它还包括第二控制信号发生器和开关单元。 通过这些布置，由于缓冲器溢出，在数据输入操作停止之后，可以从数据输入停止点重新输入光盘上的数字音频数据。

公开(公告)号：US5239636A

公开(公告)日：1993-08-24

申请号：US242743

申请日：1988-09-09

申请人： Vineet Dujari ,  Nicos Syrimis

发明人： Vineet Dujari ,  Nicos Syrimis

IPC分类号： G06F3/06 ,  G06F13/12

CPC分类号： G06F3/0601 ,  G06F13/122 ,  G06F2003/0691

摘要： A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.

公开(公告)号：US5163132A

公开(公告)日：1992-11-10

申请号：US363352

申请日：1989-06-06

申请人： Keith B. DuLac ,  Bret S. Weber

发明人： Keith B. DuLac ,  Bret S. Weber

IPC分类号： G06F3/06

CPC分类号： G06F3/0601 ,  G06F2003/0691

摘要： The present invention couples a disk drive to a small computer system interface bus by means of two buffers connected between a buffer-in bus and a buffer-out bus to allow data to be read out from a first filled buffer onto the buffer-out bus, while simultaneously permitting a filling of the second buffer from the buffer-in bus. When the second buffer is full and the first buffer is empty, the second buffer may be read while the first buffer is again filled. Toggling between the two buffers continues until the required data transfer is complete.

摘要翻译： 本发明通过连接在缓冲器总线和缓冲输出总线之间的两个缓冲器将磁盘驱动器耦合到小型计算机系统接口总线，以允许将数据从第一填充缓冲器读出到缓冲出总线 同时允许从缓冲器总线中填充第二缓冲器。 当第二缓冲器已满并且第一缓冲器为空时，可以在第一缓冲器再次被填充时读取第二缓冲器。 在两个缓冲区之间切换继续，直到所需的数据传输完成。

公开(公告)号：US5127088A

公开(公告)日：1992-06-30

申请号：US372740

申请日：1989-06-28

申请人： Toshiaki Takaki

发明人： Toshiaki Takaki

IPC分类号： G06F3/06 ,  G06F11/08 ,  G06F13/12 ,  G11B20/10 ,  G11B20/18

CPC分类号： G06F3/0601 ,  G06F11/08 ,  G06F13/122 ,  G06F2003/0691

摘要： A disk control apparatus for performing parallel data transfer between a host processor and N number of disk devices. The disk control apparatus includes N number of disk control units for controlling writing and reading of data into and from the disk devices, N number of buffer control units, each having a data buffer for storing data to be written into the disk device and data read from the disk device, and a main control unit for controlling the parallel data transfer between the host processor and the N number of buffer control units. The disk control apparatus further includes a sequential number generating unit and a check code generating unit for applying a sequential number and a check code to data to thereby write the data into the disk devices, and a comparator unit operative when transferring data stored in the data buffers which is read from the disk devices through the disk control unit for comparing sequential number and check code read from the data buffers with the sequential number and check code generated from the sequential number generating unit and check code generating unit.

摘要翻译： 一种用于在主处理器和N个盘设备之间执行并行数据传送的盘控制装置。 磁盘控制装置包括N个磁盘控制单元，用于控制从磁盘装置读取和读取数据的磁盘控制单元，N个缓冲器控制单元，每个缓冲器控制单元具有用于存储要写入盘装置的数据的数据缓冲器和数据读取 以及用于控制主处理器和N个缓冲器控制单元之间的并行数据传送的主控制单元。 盘控制装置还包括顺序号生成单元和校验码生成单元，用于将数据和校验码应用于数据，从而将数据写入到盘装置中;以及比较器单元，在传送存储在数据中的数据时可操作 通过盘控制单元从磁盘装置读取的缓冲器，用于将从数据缓冲器读取的顺序号和校验码与从序列号生成单元和校验码生成单元生成的序列号和校验码进行比较。

公开(公告)号：US5008808A

公开(公告)日：1991-04-16

申请号：US210719

申请日：1988-06-23

申请人： William J. Fries ,  Donald Kleinschnitz ,  T. Craig Nelson

发明人： William J. Fries ,  Donald Kleinschnitz ,  T. Craig Nelson

IPC分类号： G06F3/06 ,  G06F3/12 ,  G06F13/12 ,  G06K15/10

CPC分类号： G06F3/0601 ,  G06F13/126 ,  G06F3/1298 ,  G06K15/10 ,  G06F2003/0691

摘要： In a data processing system which includes a host computer connected by a channel interface unit through an input/output interface and control unit to an input/output device, commands and data associated with the commands are received in a buffer and first checked to determine whether the command has any pertinent data. If such check reveals that there is no pertinent data associated with a given command, that command is changed to an immediate command. Otherwise, the command is given a pointer in the buffer which prioritizes the order in which it will be carried out. Where a command is determined to have no pertinent data associated with such command, and a previously buffered command still in the buffer has pertinent data associated therewith, consolidation of the command immediate with the previously buffered command is carried out in order to improve efficiency of the input/output device.

摘要翻译： 在包括由通道接口单元通过输入/输出接口和控制单元连接到输入/输出设备的主计算机的数据处理系统中，在缓冲器中接收与该命令相关联的命令和数据，并且首先检查以确定是否 该命令有任何相关数据。 如果这样的检查显示没有与给定命令相关联的相关数据，则该命令被更改为立即命令。 否则，该命令给予缓冲区中的指针，该指针将优先执行其顺序。 在命令被确定为没有与这种命令相关联的相关数据的情况下，并且仍然在缓冲器中的先前缓冲的命令具有与之相关联的相关数据时，执行立即与先前缓冲的命令的命令的合并，以便提高 输入/输出设备。

公开(公告)号：US4974197A

公开(公告)日：1990-11-27

申请号：US464684

申请日：1990-01-16

申请人： Michelle K. Blount ,  Connie M. Clark ,  Warren B. Harding ,  Horace T. S. Tang

发明人： Michelle K. Blount ,  Connie M. Clark ,  Warren B. Harding ,  Horace T. S. Tang

IPC分类号： G06F3/06 ,  G06F12/08 ,  G06F17/30

CPC分类号： G06F3/0601 ,  G06F12/08 ,  G06F17/30017 ,  G06F2003/0691 ,  G06F2003/0697

摘要： Image data objects are accumulated in a relatively rapid access data buffer, such as a combination of main memory and a rapid access magnetic DASD. An optical disk recorder having a record medium with a plurality of addressable sectors each capable of storing a predetermined number of the VTOC entries receives the accumulated data objects along with the associated VTOC entries in a single access whenever the number of accumulated data objects is an inegral number of said predetermined number. A lower threshold for a minimal number of data bytes of the accumulated data objects may be required before such single access data recording operation is effected. An upper threshold of number of data bytes in the accumulated objects is also provided for causing the single access data transfer irrespective of the number of objects being an integral number of said predetermined number. The invention is advantageously practiced with a write-once, read-many record medium.

摘要翻译： 图像数据对象被累积在相对快速的访问数据缓冲器中，例如主存储器和快速访问磁DASD的组合。 具有具有多个可寻址扇区的记录介质的光盘记录器，每当能够存储预定数量的VTOC条目时，只要累积的数据对象的数目是一个单一的访问，则在一个访问中接收累积的数据对象以及相关联的VTOC条目 所述预定数量的数量。 在进行这种单次访问数据记录操作之前，可能需要累积数据对象的最小数量的数据字节的下限阈值。 还提供累积对象中的数据字节数的上限阈值，用于使得单个访问数据传送，而不管对象数是所述预定数量的整数。 本发明有利地用一次写入的多读记录介质实现。

公开(公告)号：US4956808A

公开(公告)日：1990-09-11

申请号：US54111

申请日：1987-05-20

申请人： David E. Aakre ,  Roy L. Hoffman ,  David N. Moen ,  Quentin G. Schmierer

发明人： David E. Aakre ,  Roy L. Hoffman ,  David N. Moen ,  Quentin G. Schmierer

IPC分类号： G06F3/06 ,  G06F5/06 ,  G11B20/00

CPC分类号： G06F3/0601 ,  G06F5/06 ,  G11B20/00007 ,  G06F2003/0691

摘要： A real time data transformation and transmission apparatus transforms data from a first data device and transfers the transformed data to a second data device which need not have a data transfer rate consistent with the first data device. Data from the first data device is divided into blocks and is compressed by a compression device and written into a buffer. A controller controls the buffer to transmit compressed data to the second data device as a function of the data receiving rate of the second data medium provided that the buffer contains a predetermined amount of data. While the buffer is transmitting data, the compressor is compressing further blocks of data which are being written to the buffer such that the predetermined amount of data is stored in the buffer upon completion of the buffer transmitting a block of data. This ensures that complete blocks of data are transmitted to the second data medium at the data receiving rate of the second data medium.

摘要翻译： 实时数据变换和发送装置从第一数据装置变换数据，并将转换的数据传送到不需要与第一数据装置一致的数据传送速率的第二数据装置。 来自第一数据设备的数据被划分成块并由压缩设备压缩并写入缓冲器。 作为第二数据介质的数据接收速率的函数，如果缓冲器包含预定量的数据，则控制器控制缓冲器将压缩数据传送到第二数据设备。 当缓冲器正在发送数据时，压缩器正在将进一步的正在写入缓冲器的数据块进行压缩，使得在发送数据块的缓冲器完成时将预定量的数据存储在缓冲器中。 这确保了以第二数据介质的数据接收速率将完整的数据块发送到第二数据介质。