公开(公告)号：US20050198089A1

公开(公告)日：2005-09-08

申请号：US10793920

申请日：2004-03-08

申请人： Chih-Hsiu Lin ,  An-Yeu Wu

发明人： Chih-Hsiu Lin ,  An-Yeu Wu

IPC分类号： G06F7/00

CPC分类号： G06F7/5446

摘要： A method of mixed-scaling-rotation CORDIC (MSR-CORDIC) with scaling-free rotational operations is disclosed. An elementary angles set is extended by representing the elementary angles as the arctangent of the division of two single signed-power-of-two terms to an enhanced extended elementary angles set. A combination of elementary angles is found from the enhanced extended elementary angles set such that the residue angle error can be minimized. A MSR-CORDIC operation is used to perform the rotating and scaling transformation simultaneously.

摘要翻译： 公开了一种具有无缩放旋转操作的混合缩放旋转CORDIC（MSR-CORDIC）的方法。 通过将基本角表示为将两个单个有符号幂二项分解为增强扩展基本角度集的反正切来扩展基本角度集合。 从增强的扩展基本角度集合中找到基本角度的组合，使得残余角度误差可以最小化。 MSR-CORDIC操作用于同时执行旋转和缩放转换。

公开(公告)号：US06366939B1

公开(公告)日：2002-04-02

申请号：US09504222

申请日：2000-02-15

申请人： Vitit Kantabutra

发明人： Vitit Kantabutra

IPC分类号： G06F738

CPC分类号： G06F7/5446 ,  G06F2101/04 ,  G06F2101/10

摘要： A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders {tilde over (x)}i for every “logical” iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a “physical” iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the yi's, which will eventually converge to the desired output.

摘要翻译： 用于计算指数函数的64位精密数字电路和用于计算正弦和余弦的相关64位精密数字电路，每个电路包括主电路和从电路。 主电路使用快速，低精度电路为每个“逻辑”迭代i计算余数（（x）} i），从而累积临时错误。 只有在每8个我的结尾，这标志着“物理”迭代的结束，是对所执行的累积错误的完整和快速的校正。 从电路计算称为yi的数量，最终会收敛到期望的输出。

公开(公告)号：US5317753A

公开(公告)日：1994-05-31

申请号：US667289

申请日：1991-03-11

申请人： Ronald Kuenemund ,  Tobias Noll

发明人： Ronald Kuenemund ,  Tobias Noll

IPC分类号： G06F17/16 ,  G06F7/544

CPC分类号： G06F7/5446

摘要： A CORDIC processor is provided in carry-save architecture in connection with intense pipelining for vector rotations, particularly given problems in real-time processing. The processor comprises a plurality of vector iteration stages and a plurality of angle iteration stages that are partially redundantly present in order to guarantee a convergency of the CORDIC algorithm despite an ambiguity region in the sign detection of carry-save numbers and in order to simplify other circuit components, for example a multiplier. As a result of the carry-save architecture, only incomplete addition/subtraction operations are executed in the iteration stages, and intermediate results in the form of carry and save words are fed through the CORDIC processor on separate line paths until they are added in an adder at the processor output to form the final result vector. The invention is advantageous in the low chip surface requirement that results from a high regularity of the overall structure and from simply-constructed base cells of the vector and angle iteration stages and in the extremely-high processing speed that results from the combination of intense pipelining and the carry-save architecture.

摘要翻译： CORDIC处理器在携带保存架构中提供了与用于向量旋转的强流水线相关联，特别是在实时处理中给定的问题。 处理器包括多个矢量迭代阶段和多个角度迭代阶段，其部分冗余存在，以便保证CORDIC算法的可收敛性，尽管在进位保存号码的符号检测中存在模糊区域，并且为了简化其他 电路组件，例如乘法器。 作为进位保存架构的结果，在迭代阶段仅执行不完全的加法/减法操作，并且以进位和保存字的形式的中间结果通过CORDIC处理器在单独的线路路径上馈送，直到它们被添加到 加法器处理器输出以形成最终的结果向量。 本发明在低的芯片表面要求方面是有利的，这是由于整体结构的高规整性和简单构建的矢量和角度迭代阶段的基体以及极高的处理速度导致的， 和进位保存架构。

公开(公告)号：US5134578A

公开(公告)日：1992-07-28

申请号：US685340

申请日：1991-04-15

申请人： Steven L. Garverick ,  Kenji Fujino

发明人： Steven L. Garverick ,  Kenji Fujino

IPC分类号： G01R19/00 ,  G01R21/00 ,  G01R21/133 ,  G05B19/042 ,  G06F7/544 ,  G06F15/78 ,  G06F17/10

CPC分类号： G06F15/7842 ,  G05B19/0423 ,  G06F7/5443 ,  G06F7/5446 ,  G01R21/006 ,  G05B2219/25254

摘要： A bit-serial processor for selectively carrying out the sequential steps of performing by successive approximations Coordinate Rotation Digital Computation (CORDIC), non-restoring division or non-restoring square rooting calculations is suitable for inclusion in a monolithic integrated circuit with a plurality of sensors for generating respective sensor output signals, circuitry for converting each sensor output signal to bit-serial digital format, and a bit-serial muliptly-add processor. Together with an electrically-erasable programmable read-only memory and a plurality of current transformers, the monolithic integrated circuit implements a system for metering a-c power main conductors.

摘要翻译： 用于选择性地执行通过逐次逼近执行的顺序步骤的位串行处理器坐标旋转数字计算（CORDIC），非恢复分割或非恢复平方根生根计算适用于包含在具有多个传感器的单片集成电路 用于产生相应的传感器输出信号，用于将每个传感器输出信号转换为比特串行数字格式的电路和一个位串行多媒体加法处理器。 与电可擦除可编程只读存储器和多个电流互感器一起，单片集成电路实现用于计量a-c电源主导体的系统。

公开(公告)号：US4899302A

公开(公告)日：1990-02-06

申请号：US311168

申请日：1989-02-15

申请人： Misayo Nakayama

发明人： Misayo Nakayama

IPC分类号： G06F7/548 ,  G06F7/544

CPC分类号： G06F7/5446

摘要： An arithmetic unit carries out sequentially arithmetic pseudo division and reverse-sequentially arithmetic pseudo multiplication according to algolithm based on CORDIC method utilizing constant values 2.sup.k xarctan(2.sup.-k) so as to calculate value of inverse trigonometric function arctan y/x. A generater sequentially generates constant values 2.sup.k xarctan(2.sup.-k) from k=m-1 to k=0 where k=0, 1, . . . , m-1. A first register is operable during the pseudo division for storing a first variable and operable during the pseudo multiplication for storing a destined variable. A second register is operable during the pseudo division for storing a second variable. A barrel shifter right-shifts the value of second variable by a given shaft bit count 2k where k=1, 2, . . . , m-2, m-1, m. A first adder-subtracter operates during the psuedo division for selectively adding or subtracting the right-shifted value of second variable to or from the value of first variable to output the result into the first register to thereby update the value of first variable, and operates during the pseudo multiplication for selectively adding or subtracting the constant value of generator to or from the value of destined variable stored in the first register to output the result into the first register to thereby update the value of destined variable. A second adder-subtracter operates during the pseudo division for selectively adding or subtracting the value of first variable to or from the value of second variable to output the result into the second register to thereby update the value of second variable. An m-stage stacker operates to process a sign bit of the second variable in First-In, Last-Out basis for controlling the first and second adder-subtracters to selectively carry out adding or subtracting operation.

摘要翻译： 算术单元根据使用常数2kxarctan（2-k）的CORDIC方法，根据算法进行依次运算的伪分割和反向顺序算术伪乘法，以计算反三角函数arctan y / x的值。 发生器顺序地从k = m-1到k = 0生成恒定值2kxarctan（2-k），其中k = 0,1，...。 。 。 ，m-1。 在伪划分期间，第一寄存器可操作用于存储第一变量，并且在伪乘法期间可操作以存储目标变量。 在伪划分期间，第二寄存器可操作以存储第二变量。 桶形移位器通过给定的轴位数2k右移第二个变量的值，其中k = 1,2。 。 。 ，m-2，m-1，m。 第一加减法器在伪零分割期间操作，用于选择性地将第二变量的右移值与第一变量的值相加或减去，以将结果输出到第一寄存器，从而更新第一变量的值，并且操作 在伪乘法期间，用于选择性地将发生器的常数值与存储在第一寄存器中的目标变量的值相加或减去，以将结果输出到第一寄存器，从而更新目标变量的值。 第二加法器减法器在伪分割期间操作，用于选择性地将第一变量的值加到或从第二变量的值中减去第二变量的值，以将结果输出到第二寄存器，从而更新第二变量的值。 m级堆叠器用于处理第一变量，第一和最后输出的第二变量的符号位，用于控制第一和第二加减法器选择性地执行加法或减法运算。

公开(公告)号：US09973360B2

公开(公告)日：2018-05-15

申请号：US15366273

申请日：2016-12-01

申请人： NXP USA, Inc.

发明人： Olivier Vincent Doare ,  Dominique Delbecq ,  Gilles Montoriol

IPC分类号： H04L27/00 ,  G06F7/544 ,  G06F7/548 ,  H04L27/20

CPC分类号： H04L27/0014 ,  G06F7/5446 ,  G06F7/548 ,  H04L27/206 ,  H04L2027/0016

摘要： A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value θ1, receive a second phase value θ2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value θ1, and compute a second digital phase shift control value based on the received second phase value θ2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.

公开(公告)号：US20180017411A1

公开(公告)日：2018-01-18

申请号：US15646357

申请日：2017-07-11

申请人： TDK - Micronas GmbH

发明人： Juergen Huppertz

IPC分类号： G01D5/14 ,  G01R33/07

CPC分类号： G01D5/145 ,  G01R33/07 ,  G06F7/5446

摘要： A method and system for computing the phase shift or the amplitude of an electromagnetic three-phase system. The method comprises the following steps of: detecting vector values corresponding to an electromagnetic quantity by three sensors, the three sensors delivering signals that are offset from each other substantially by 0°, 120° and 240°; computing changed vector values by logically adjusting one of the detected vector values to a phase of 0°; and iteratively computing the phase shift of the three-phase system using the changed vector values.

公开(公告)号：US20150355885A1

公开(公告)日：2015-12-10

申请号：US14729410

申请日：2015-06-03

申请人： CANON KABUSHIKI KAISHA

发明人： Tadayoshi Nakayama ,  Koki Mitsunami

IPC分类号： G06F7/544 ,  G06F17/10

CPC分类号： G06F7/5446 ,  G06F17/16 ,  G06F2207/3884

摘要： An arithmetic apparatus comprises a plurality of cascade-connected arithmetic units. Each of the plurality of arithmetic units comprises: a calculator configured to operate in one of a rotation mode of performing a rotation calculation, and a vectoring mode of calculating a rotation angle; and a holding unit configured to hold rotational direction information output from the calculator in the vectoring mode. In addition, when operating in the rotation mode, the calculator performs the rotation calculation on data input from an arithmetic unit in a preceding stage, based on the rotational direction information held in the holding unit.

摘要翻译： 运算装置包括多个级联连接的算术单元。 所述多个算术单元中的每一个包括：运算器，被配置为在执行旋转运算的旋转模式和运算旋转角度的矢量运算模式中进行运算; 以及保持单元，被配置为保持在向量化模式中从计算器输出的旋转方向信息。 此外，当在旋转模式下操作时，计算器基于保持在保持单元中的旋转方向信息，对在前一级中的运算单元输入的数据进行旋转计算。

公开(公告)号：US09021003B2

公开(公告)日：2015-04-28

申请号：US13805519

申请日：2011-06-16

申请人： Katsutoshi Seki

发明人： Katsutoshi Seki

IPC分类号： G06F17/14 ,  G06F7/548 ,  G06F7/544

CPC分类号： G06F7/548 ,  G06F7/5446 ,  G06F17/141

摘要： Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

摘要翻译： 公开了一种处理器，即使在非DFT操作处理期间也能够有效地执行DFT操作而不使基本操作电路的一部分空闲。 处理器（1）具有操作装置（操作单元）（2）和控制装置（控制单元）（3）。 操作装置（2）具有连接使得可以执行CORDIC（协调旋转二进制计算机）操作的多个移位加法和减法装置。 移位加减法装置还执行处理一级以上的移位加减法的蝶形运算的移位加法运算处理。 控制装置（3）基于从外部接收的多个数据指示操作装置（2）执行CORDIC操作或蝶形操作。

公开(公告)号：US20130097214A1

公开(公告)日：2013-04-18

申请号：US13805519

申请日：2011-06-16

申请人： Katsutoshi Seki

发明人： Katsutoshi Seki

IPC分类号： G06F7/548

CPC分类号： G06F7/548 ,  G06F7/5446 ,  G06F17/141

摘要： Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

摘要翻译： 公开了一种处理器，即使在非DFT操作处理期间也能够有效地执行DFT操作而不使基本操作电路的一部分空闲。 处理器（1）具有操作装置（操作单元）（2）和控制装置（控制单元）（3）。 操作装置（2）具有连接使得可以执行CORDIC（协调旋转二进制计算机）操作的多个移位加法和减法装置。 移位加减法装置还执行处理一级以上的移位加减法的蝶形运算的移位加法运算处理。 控制装置（3）基于从外部接收的多个数据指示操作装置（2）执行CORDIC操作或蝶形操作。