公开(公告)号：US09530425B2

公开(公告)日：2016-12-27

申请号：US14217234

申请日：2014-03-17

Applicant: Digital Intelligence, L.L.C.

Inventor： Carlos A. Ricci ,  Vladimir V. Kovtun

IPC: G10L19/26 ,  H03H17/02 ,  A61B5/0432 ,  G01V1/28

CPC classification number: G10L19/26 ,  A61B5/0432 ,  G01V1/28 ,  G01V2210/43 ,  H03H17/0201 ,  H03H17/0248 ,  H03H17/0266

Abstract: A system and method for representing quasi-periodic (“qp”) waveforms, for example, representing a plurality of limited decompositions of the qp waveform. Each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. Data-structure attributes are created and used to reconstruct the qp waveform. Features of the qp wave are tracked using pattern-ecognition techniques. The fundamental rate of the signal (e.g., heartbeat) can vary widely, for example by a factor of 2-3 or more from the lowest to highest frequency. To get quarter-phase representations of a component (e.g., lowest frequency “rate” component) that varies over time (by a factor of two to three) many overlapping filters use bandpass and overlap parameters that allow tracking the component's frequency version on changing quarter-phase basis.

Abstract translation: 用于表示准周期（“qp”）波形的系统和方法，例如，表示qp波形的多个限制分解。 每个分解包括第一和第二振幅值和至少一个时间值。 在一些实施例中，每个分解被相位调整，使得多个有限分解的算术和重建qp波形。 数据结构属性被创建并用于重建qp波形。 使用模式识别技术跟踪qp波的特征。 信号的基本速率（例如，心跳）可以广泛地变化，例如从最低频率到最高频率的2-3倍或更多倍。 为了获得随时间变化的分量（例如，最低频率“速率”分量）的四分之一相位表示（两倍至三倍），许多重叠滤波器使用带通和重叠参数，允许在变化的季度跟踪组件的频率版本 的基础。

公开(公告)号：US09449608B2

公开(公告)日：2016-09-20

申请号：US14306495

申请日：2014-06-17

Applicant: Dolby International AB

Inventor： Per Ekstrand

IPC: G06F17/10 ,  G10L21/00 ,  H03H17/02

CPC classification number: H04R3/04 ,  G06F17/10 ,  G06F17/11 ,  G10L19/008 ,  G10L19/0204 ,  G10L19/0208 ,  G10L19/26 ,  G10L19/265 ,  G10L21/00 ,  H03H17/0201 ,  H03H17/0248 ,  H03H17/0266 ,  H03H17/0275 ,  H03H17/0294 ,  H03H2017/0297 ,  H04S7/307

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems.

公开(公告)号：US20140304315A1

公开(公告)日：2014-10-09

申请号：US14306495

申请日：2014-06-17

Applicant: Dolby International AB

Inventor： Per Ekstrand

IPC: H03H17/02

CPC classification number: H04R3/04 ,  G06F17/10 ,  G06F17/11 ,  G10L19/008 ,  G10L19/0204 ,  G10L19/0208 ,  G10L19/26 ,  G10L19/265 ,  G10L21/00 ,  H03H17/0201 ,  H03H17/0248 ,  H03H17/0266 ,  H03H17/0275 ,  H03H17/0294 ,  H03H2017/0297 ,  H04S7/307

Abstract: The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems.

Abstract translation: 该文件涉及调制的次采样数字滤波器组，以及用于设计这种滤波器组的方法和系统。 特别地，本文件提出了一种用于改进低延迟调制数字滤波器组的方法和装置。 该方法采用非对称低通原型滤波器的调制和用于优化滤波器系数的新方法。 此外，给出了使用640系数的原型滤波器长度和319个采样的系统延迟的64信道滤波器组的具体设计。 该方法基本上减少了由于子带信号的独立修改引起的混叠所产生的伪像，例如当使用滤波器组作为频谱均衡器时。 该方法优选地以在标准PC或数字信号处理器（DSP）上运行的软件实现，但也可以在定制芯片上被硬编码。 该方法为各种类型的数字均衡器，自适应滤波器，多频带压缩器和用于高频重建（HFR）或参数立体声系统的频谱包络调整滤波器组提供了改进。

公开(公告)号：US20140278382A1

公开(公告)日：2014-09-18

申请号：US14217317

申请日：2014-03-17

Applicant: DIGITAL INTELLIGENCE, L.L.C.

Inventor： Carlos A. Ricci ,  Vladimir V. Kovtun

IPC: G10L19/26

CPC classification number: G10L19/26 ,  A61B5/0432 ,  G01V1/28 ,  G01V2210/43 ,  H03H17/0201 ,  H03H17/0248 ,  H03H17/0266

Abstract: A system and method for representing quasi-periodic waveforms, for example, representing a plurality of limited decompositions of the quasi-periodic waveform. Each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the quasi-periodic waveform. Data-structure attributes are created and used to reconstruct the quasi-periodic waveform. Features of the quasi-periodic wave are tracked using pattern-recognition techniques. The fundamental rate of the signal (e.g., heartbeat) can vary widely, for example by a factor of 2-3 or more from the lowest to highest frequency. To get quarter-phase representations of a component (e.g., lowest frequency “rate” component) that varies over time (by a factor of two to three) many overlapping filters use bandpass and overlap parameters that allow tracking the component's frequency version on changing quarter-phase basis.

Abstract translation: 用于表示准周期波形的系统和方法，例如，表示准周期波形的多个有限分解。 每个分解包括第一和第二振幅值和至少一个时间值。 在一些实施例中，每个分解被相位调整，使得多个有限分解的算术和重建准周期波形。 数据结构属性被创建并用于重构准周期波形。 使用模式识别技术跟踪准周期波的特征。 信号的基本速率（例如，心跳）可以广泛地变化，例如从最低频率到最高频率的2-3倍或更多倍。 为了获得随时间变化的分量（例如，最低频率“速率”分量）的四分之一相位表示（两倍至三倍），许多重叠滤波器使用带通和重叠参数，允许在变化的季度跟踪组件的频率版本 的基础。

公开(公告)号：US20140195577A1

公开(公告)日：2014-07-10

申请号：US14159033

申请日：2014-01-20

Applicant: Avatekh, Inc.

Inventor： Alexei V. Nikitin

IPC: H03H17/02

CPC classification number: H03H17/0219 ,  H03H7/0153 ,  H03H11/1256 ,  H03H11/1291 ,  H03H11/24 ,  H03H17/0201 ,  H03H21/0001 ,  H03H21/0016 ,  H03H2210/043 ,  H03M1/1235

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis. The NDL-based filtering method and apparatus enable improvements in the overall properties of electronic devices including, but not limited to, improvements in performance, reduction in size, weight, cost, and power consumption, and, in particular for wireless devices, NDLs enable improvements in spectrum usage efficiency.

Abstract translation: 本发明涉及非线性信号处理，特别涉及利用模拟非线性差分限幅器（NDL）的实数，复数和向量值信号的自适应非线性滤波，以及自适应实时信号调理，处理， 分析，量化，比较和控制。 更一般地，本发明涉及用于实时测量和分析变量以及通用测量系统和过程的方法，过程和装置。 本发明还涉及用于测量的方法和相应的装置，其延伸到不同的应用并且提供除变量的瞬时值之外的结果。 本发明还涉及测量变量的后处理分析和统计分析。 基于NDL的滤波方法和装置能够改进电子设备的整体特性，包括但不限于性能的改善，尺寸，重量，成本和功耗的减小，特别是对于无线设备，NDL使得能够 频谱使用效率的提高。

公开(公告)号：US08478807B2

公开(公告)日：2013-07-02

申请号：US11895538

申请日：2007-08-24

Applicant: Thomas E. Curtis ,  Steven B. Sidman

Inventor： Thomas E. Curtis ,  Steven B. Sidman

IPC: G06F17/10

CPC classification number: H03H17/0201

Abstract: Digital signal-processing structure and methodology which feature a time-slice-based digital fabricating engine, and software operating structure operatively associated with that engine structured to operate the engine in a time-slice-based fabrication mode wherein the engine, in a time-differentiated and instantiating manner, functions to fabricate a time-succession of individual, composite wave digital filters. Each of these filters takes the form of (1) a concatenated assembly including one to a plurality of upstream, early-stage, decimate-by-two, signal-processing agencies connected in a cascade series arrangement, with each such agency possessing a first transfer function having a first transition bandwidth, and (2) a single, downstream, later-stage, decimate-by-two, signal-processing agency which possesses a second transfer function having a transition bandwidth which is less than the mentioned first transition bandwidth.

Abstract translation: 具有基于时间片的数字制造引擎的数字信号处理结构和方法，以及与该引擎可操作地相关联的软件操作结构，其被构造为以时间片为基础的制造模式来操作发动机，其中， 具有差异化和实例化的功能，用于制造单个复合波数字滤波器的时间序列。 这些过滤器中的每个过滤器采取以下形式：（1）包括以级联系列排列连接的一个到多个上游，早期，抽搐，信号处理机构的级联组件，每个这样的机构具有第一 具有第一过渡带宽的传递函数，以及（2）具有第二传递函数的单个，下游，后级，二进制信号处理机构，其具有小于所述第一过渡带宽的转换带宽 。

公开(公告)号：US5754455A

公开(公告)日：1998-05-19

申请号：US631321

申请日：1996-04-10

Applicant: James Clark Baker ,  Denise Carol Riemer

Inventor： James Clark Baker ,  Denise Carol Riemer

IPC: H03H17/02 ,  G06F17/10

CPC classification number: H03H17/0201

Abstract: Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.

Abstract translation: 位串行数字滤波器使用大量触发器，必须将其复位到已知的全零状态，以便测试和启动目的。 将位串行数字滤波器设置为全零状态的方法使用不可复位触发器，这消除了可复位触发器的增加的栅极数和电流消耗开销。 使用非可复位触发器（例如简单的不可复位D触发器）来构造位串行数字滤波器。 当启动复位信号时，复位控制器（350）将全零信号发送到位于数字滤波器的输入端和每个反馈回路或单位延迟路径中的复位门（301,321）。 同时，位串行控制器（250）循环其控制信号以模拟位串行滤波器的操作。 在两个字周期中，数字滤波器中的每个触发器将被设置为已知的全零状态，并且全零信号被去除以允许滤波器的正常操作。

公开(公告)号：US4825396A

公开(公告)日：1989-04-25

申请号：US14258

申请日：1987-02-12

Applicant: Lajos Gazsi

Inventor： Lajos Gazsi

IPC: H03H17/00 ,  H03H17/02 ,  G06F15/31

CPC classification number: H03H17/0201

Abstract: A digital circuit for sampling rate variation and signal filtering includes an input, an output, a lattice wave digital filter having a plurality of filter branches connected to the input, the filter branches each having at least two series-connected filter subgroups with basic filter elements each formed of one two port adaptor made up of adders and multipliers and one time-lag device, a device disposed between the at least two filter subgroups for varying the sampling rate and for generating a phase change in a digital system, and an adder connected between filter branches and the output. A method for constructing the circuit is also provided.

Abstract translation: 用于采样率变化和信号滤波的数字电路包括输入，输出，具有连接到输入的多个滤波器分支的格子波数字滤波器，每个滤波器分支具有至少两个具有基本滤波器元件的串联滤波器子组 每个由一个由加法器和乘法器组成的两个端口适配器和一个时间延迟器件形成，一个设置在该至少两个滤波器子组之间用于改变采样率并用于在数字系统中产生相位变化的装置，以及一个加法器 在过滤器分支和输出之间。 还提供了一种用于构建电路的方法。

公开(公告)号：US4716537A

公开(公告)日：1987-12-29

申请号：US592799

申请日：1984-03-23

Applicant: Helmut Scheuermann

Inventor： Helmut Scheuermann

IPC: H03H17/02 ,  G06F7/38

CPC classification number: H03H17/0201

Abstract: A wave two port circuit arrangement for simulating a resistive elementary port two device for use in a wave digital filter. First and second ports are each arranged for receiving input and output signals. A summing device is connected to the first and second ports and produces a sum signal which represents the sum of the input signals present at the first and second ports. A multiplier is connected to the summing device and to one of the first and second ports for producing a negatively scaled sum signal and feeding it to the one port as part of the output signal present at that port.

Abstract translation: 用于模拟用于波数字滤波器的电阻性基本端口两个装置的波形两端口电路装置。 第一和第二端口每个被布置用于接收输入和输出信号。 求和装置连接到第一和第二端口，并产生表示第一和第二端口处存在的输入信号之和的和信号。 乘法器连接到求和装置和第一和第二端口中的一个端口，用于产生负向量化的和信号，并将其馈送到作为在该端口处的输出信号的一部分的一个端口。

公开(公告)号：US4061905A

公开(公告)日：1977-12-06

申请号：US672884

申请日：1976-04-02

Applicant: Alfred Fettweis

Inventor： Alfred Fettweis

IPC: H03H17/02 ,  G06F15/34 ,  H03H7/10

CPC classification number: H03H17/0201

Abstract: In one illustrative embodiment, a filter circuit for discrete signals is provided corresponding in filter function to an analog ladder structure containing inductive and capacitive components. The reactive components of the analog filter structure are realized in the filter circuit as one-port and two-port elements having time delay, while nonreactive components of the analog filter are realized as time-delay-free one-port and plural-port elements. Interface means connect the port elements together in a configuration corresponding to the configuration of the analog ladder structure, with sets of adder and multiplier means of the interface circuitry which couple successive sets of the port elements to each other being correlated with the connective relationship (whether series, series-parallel or parallel) between the corresponding components or branches of the analog ladder structure and with the parameters of the analog components, so that the filter circuit essentially simulates the analog ladder structure in its filter characteristics.

Abstract translation: 在一个说明性实施例中，用于离散信号的滤波器电路在滤波器功能中被提供给包含电感和电容分量的模拟梯形结构。 模拟滤波器结构的无功分量在滤波电路中实现为具有时间延迟的单端口和双端口元件，而模拟滤波器的非反应分量被实现为无延时的单端口和多端口元件 。 接口意味着以对应于模拟梯形结构的配置的配置将端口元件连接在一起，使得将连续的端口元件组彼此耦合的接口电路的加法器和乘法器装置的集合与连接关系相关 串并联或并联）在模拟梯形结构的相应组件或分支之间以及模拟组件的参数，使得滤波器电路基本上模拟其滤波器特性中的模拟梯形结构。