公开(公告)号：US11897539B2

公开(公告)日：2024-02-13

申请号：US17032394

申请日：2020-09-25

Applicant: Seiko Epson Corporation

Inventor： Hideo Haneda

IPC: B62D11/00 ,  H03M1/44 ,  H03M1/12 ,  G04F10/00

CPC classification number: B62D11/003 ,  G04F10/005 ,  H03M1/1235 ,  H03M1/442

Abstract: The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the second integration polarity switching signal in the first integration period.

公开(公告)号：US09929739B1

公开(公告)日：2018-03-27

申请号：US15613625

申请日：2017-06-05

Applicant: THE BOEING COMPANY

Inventor： Alfio Zanchi

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/08

CPC classification number: H03M1/1033 ,  H03M1/0612 ,  H03M1/0663 ,  H03M1/0863 ,  H03M1/1019 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1235

Abstract: A method of determining Integral Non-Linearity (INL) of an Analog-to-Digital Converter (ADC) is provided. The method includes providing an input signal to the ADC, phase-locking a clock signal of a clock of the ADC to the input signal, generating a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, applying averaging to the plurality of samples for each sampled phase to generate a reconstructed ADC output signal, and determining the INL of the ADC based on a comparison of the reconstructed ADC output signal to a theoretical ADC output signal.

公开(公告)号：US09467113B2

公开(公告)日：2016-10-11

申请号：US14159033

申请日：2014-01-20

Applicant: Avatekh, Inc.

Inventor： Alexei V. Nikitin

IPC: G06G7/02 ,  H03H7/01 ,  H03H11/12 ,  H03H21/00 ,  H03H11/24

CPC classification number: H03H17/0219 ,  H03H7/0153 ,  H03H11/1256 ,  H03H11/1291 ,  H03H11/24 ,  H03H17/0201 ,  H03H21/0001 ,  H03H21/0016 ,  H03H2210/043 ,  H03M1/1235

Abstract: The present invention relates to nonlinear signal processing, and, in particular, to adaptive nonlinear filtering of real-, complex-, and vector-valued signals utilizing analog Nonlinear Differential Limiters (NDLs), and to adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. More generally, this invention relates to methods, processes and apparatus for real-time measuring and analysis of variables, and to generic measurement systems and processes. This invention also relates to methods and corresponding apparatus for measuring which extend to different applications and provide results other than instantaneous values of variables. The invention further relates to post-processing analysis of measured variables and to statistical analysis. The NDL-based filtering method and apparatus enable improvements in the overall properties of electronic devices including, but not limited to, improvements in performance, reduction in size, weight, cost, and power consumption, and, in particular for wireless devices, NDLs enable improvements in spectrum usage efficiency.

公开(公告)号：US09276599B2

公开(公告)日：2016-03-01

申请号：US14446107

申请日：2014-07-29

Applicant: The Boeing Company

Inventor： Amir Leon Liaghati

IPC: H03M1/12

CPC classification number: H03M1/12 ,  H03M1/121 ,  H03M1/1235 ,  H03M1/188

Abstract: A method and apparatus for converting an analog input into a final digital output. A first digital output is generated in response to receiving an analog input at a first converter. A second digital output is generated in response to receiving the analog input at a second converter. The first digital output is output to form the final digital output when an amplitude of the analog input is within a first portion of an overall range of amplitudes for the analog input and the second digital output is output to form the final digital output when the amplitude is within a second portion of the overall range of amplitudes.

Abstract translation: 一种用于将模拟输入转换成最终数字输出的方法和装置。 响应于在第一转换器处接收模拟输入而产生第一数字输出。 响应于在第二转换器处接收模拟输入而产生第二数字输出。 当模拟输入的幅度在模拟输入的幅度的整个范围的第一部分内时，第一数字输出被输出以形成最终的数字输出，并且当幅度的幅度输出时，第二数字输出被输出以形成最终的数字输出 在整个幅度范围的第二部分内。

公开(公告)号：US08653997B2

公开(公告)日：2014-02-18

申请号：US13724299

申请日：2012-12-21

Applicant: Fujitsu Semiconductor Limited

Inventor： Uichi Sekimoto

IPC: H03M3/00

CPC classification number: H03M1/1235 ,  H03M3/39 ,  H03M3/434 ,  H03M3/456

Abstract: A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.

Abstract translation: 将第一信号量化为具有多个位的量化信号的调制器包括在第一周期内对第一信号执行采样的积分器，并且在第二周期中对第一信号和参考信号之间的差进行积分; 以及量化器，接收作为所述积分器的输出并与具有比所述第一周期短的周期的第一时钟同步地操作的第二信号，所述量化器基于所述第一时段中的所述第二信号生成所述量化信号，并输出 基于向积分器的量化信号的参考信号。

公开(公告)号：US08618973B2

公开(公告)日：2013-12-31

申请号：US13382735

申请日：2010-07-08

Applicant: Bob Verbruggen

Inventor： Bob Verbruggen

IPC: H03M1/44 ,  H03M1/14

CPC classification number: H03M1/002 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1235 ,  H03M1/164 ,  H03M1/361 ,  H03M1/445

Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.

Abstract translation: 本发明涉及一种用于将模拟输入信号转换成数字信号的流水线模数转换器ADC，该数字信号包括：具有可调阈值的多个比较装置，用于比较输入信号; 所述给定阈值中的至少两个是不同的，以及多个放大电路，其中所述多个比较装置被配置为形成分级树结构，所述分级树结构具有多个层级，其中至少一个所述 层级与所述多个放大电路中的至少一个放大电路相关联，所述至少一个放大电路在下一层级产生至少一个比较装置的输入，其中所述多个层级包括用于设置所述多个放大电路的装置， 根据先前层次级别的输出，可调整的阈值，从而消除前一级别级别的非线性失真。

公开(公告)号：US20130194125A1

公开(公告)日：2013-08-01

申请号：US13724299

申请日：2012-12-21

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Uichi SEKIMOTO

IPC: H03M1/12

CPC classification number: H03M1/1235 ,  H03M3/39 ,  H03M3/434 ,  H03M3/456

Abstract: A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.

Abstract translation: 将第一信号量化为具有多个位的量化信号的调制器包括在第一周期内对第一信号执行采样的积分器，并且在第二周期中对第一信号和参考信号之间的差进行积分; 以及量化器，接收作为所述积分器的输出并与具有比所述第一周期短的周期的第一时钟同步地操作的第二信号，所述量化器基于所述第一时段中的所述第二信号生成所述量化信号，并输出 基于向积分器的量化信号的参考信号。

公开(公告)号：US08378872B2

公开(公告)日：2013-02-19

申请号：US13077132

申请日：2011-03-31

Applicant: Jason H. Rud ,  Andrew J. Bronczyk

Inventor： Jason H. Rud ,  Andrew J. Bronczyk

IPC: H03M1/12

CPC classification number: H03M1/20 ,  H03M1/1235 ,  H03M1/181

Abstract: A process variable transmitter is used to measure a process variable, and, in doing so, dynamically changes the resolution of the A/D converter based upon the measured value of the analog input signal. This can be done by automatically adjusting the configurable resolution gain adjustment based on the value of the analog signal being measured, by normalizing the input signal being measured so that it is centered in an optimal resolution window of the A/D converter, or by adjusting a voltage reference provided to the A/D converter.

公开(公告)号：US08199043B2

公开(公告)日：2012-06-12

申请号：US12863149

申请日：2009-01-22

Applicant: Geert Van der Plas ,  Bob Verbruggen

Inventor： Geert Van der Plas ,  Bob Verbruggen

IPC: H03M1/38

CPC classification number: H03M1/125 ,  H03M1/002 ,  H03M1/1235 ,  H03M1/361 ,  H03M1/42

Abstract: An analog-to-digital converter that uses a comparator based asynchronous binary search is described. The architecture includes a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator only, for example to the first or root comparator. The at least one comparator is further arranged for controlling at least one other comparator of the plurality of comparators.

Abstract translation: 描述了使用基于比较器的异步二进制搜索的模数转换器。 该架构包括比较器的自定时（异步）分层二进制树，每个被布置成具有预定阈值。 输入信号与闪存转换器的情况并行地应用于所有比较器，但是时钟仅施加到（至少）一个比较器，例如到第一个或根比较器。 所述至少一个比较器还被布置用于控制所述多个比较器中的至少一个其它比较器。

公开(公告)号：US08077068B2

公开(公告)日：2011-12-13

申请号：US12730435

申请日：2010-03-24

Applicant: David LaChartre

Inventor： David LaChartre

IPC: H03M1/12

CPC classification number: H03M1/34 ,  H03M1/1235 ,  H03M1/125

Abstract: The invention relates to an N-bit asynchronous Quantizer including a 2N−1 signal amplifier stages (G12-G2N−12) arranged in series, the input of the first stage being capable of receiving a signal to be quantized; 2N−1 comparators (C12-C2N−12), one comparator being connected to the output of each amplifier stage (G12-G2N−12), and capable of comparing the value of this output with a predetermined threshold value; and at least 2N−2 delay lines (D12-D2N−12) placed at the output of the 2N−2 first comparators, the signals supplied at the output of the delay lines (D12-D2N−12) and of the last comparator constituting at any instant the quantized binary values of the input signal with a time shift.

Abstract translation: 本发明涉及一种包括串联布置的2N-1个信号放大级（G12-G2N-12）的N位异步量化器，该第一级的输入能够接收待量化的信号; 2N-1比较器（C12-C2N-12），一个比较器连接到每个放大器级（G12-G2N-12）的输出，并且能够将该输出的值与预定阈值进行比较; 以及放置在2N-2个第一比较器的输出处的至少2N-2个延迟线（D12-D2N-12），在延迟线（D12-D2N-12）的输出处提供的信号和最后的比较器 在任何时刻，具有时移的输入信号的量化二进制值。