公开(公告)号：US08850394B2

公开(公告)日：2014-09-30

申请号：US12437081

申请日：2009-05-07

申请人： David Alan Edwards

发明人： David Alan Edwards

IPC分类号： G06F9/44 ,  G06F11/00 ,  G06F19/00 ,  G06F11/36

CPC分类号： G06F11/3636

摘要： A method and processor for debugging a target processor. The method comprises: executing code on the target processor to generate trace information for debugging; and during execution of that code, periodically incrementing a value of a counter on the target processor. The execution of the code includes executing a plurality of timestamp instructions on the target processor each to associate a respective timestamp with the trace information. The execution of each timestamp instruction comprises generating the respective timestamp by reading the value of the counter into a software accessible storage location and subsequently resetting the counter.

摘要翻译： 用于调试目标处理器的方法和处理器。 该方法包括：执行目标处理器上的代码生成跟踪信息进行调试; 并且在该代码的执行期间，周期性地增加目标处理器上的计数器的值。 代码的执行包括在目标处理器上执行多个时间戳指令以将相应的时间戳与跟踪信息相关联。 每个时间戳指令的执行包括通过将计数器的值读取到软件可访问存储位置中并随后重置计数器来生成相应的时间戳。

公开(公告)号：US08724736B2

公开(公告)日：2014-05-13

申请号：US13062604

申请日：2009-09-08

申请人： Abdellatif Bellaouar ,  See Taur Lee ,  Sher Jiun Fang ,  Sherif H. K. Embabi ,  Tajinder Manku

发明人： Abdellatif Bellaouar ,  See Taur Lee ,  Sher Jiun Fang ,  Sherif H. K. Embabi ,  Tajinder Manku

IPC分类号： H04L25/49

CPC分类号： H03F3/245 ,  H03F1/0261 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/45659 ,  H03F3/72 ,  H03F2200/372 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2203/21142 ,  H03F2203/21175 ,  H03F2203/21178 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45544 ,  H03F2203/45634 ,  H03F2203/45726 ,  H03F2203/7236 ,  H03G3/001

摘要： A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.

摘要翻译： 具有覆盖WCDMA / EDGE / GSM应用的单个信号路径或硬件的发射机架构，并且在发射机输出端不需要SAW。 发射机架构允许发送收敛功能。 具有独特驱动器的无源混频器，此外还可使用CMOS工艺的混频器内核提供的本机器件，可实现低电压和低功耗设计，低输出噪声和高线性度。 数字可变增益放大器具有覆盖从低电源电压操作的宽输出动态范围并与没有DAC的基带电路数字接口的能力。 单个变压器用于组合来自WCDMA / EDGE和GSM驱动器的输出，随后将差分信号路径转换为单端信号。 RF开关用于将变压器的输出转移到不同的频带和应用。

公开(公告)号：US08689197B2

公开(公告)日：2014-04-01

申请号：US12572836

申请日：2009-10-02

申请人： David Alan Edwards ,  Alan Alexander

发明人： David Alan Edwards ,  Alan Alexander

IPC分类号： G06F9/45

CPC分类号： G06F8/4442 ,  G06F8/54

摘要： Disclosed herein is a method of optimizing an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behavior of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimizing an executable program. A linker product and a computer program are also disclosed.

摘要翻译： 这里公开了一种优化可执行程序以在处理器上执行时提高指令高速缓存命中率的方法。 还公开了一种预测可执行程序的指令高速缓存行为的方法。 根据本发明的另一方面，提供了一种包括代码的软件开发工具产品，其在计算机上执行时将执行优化可执行程序的方法。 还公开了接头产物和计算机程序。

公开(公告)号：US08654821B2

公开(公告)日：2014-02-18

申请号：US13896522

申请日：2013-05-17

申请人： Icera, Inc.

发明人： Hamid Safiri

IPC分类号： H04B1/38

CPC分类号： H04L25/03853

摘要： A fractional rate converting filter in a wireless transceiver comprising a delay line, multiplier circuit, adder circuit, and selector. The delay line receives a digital input signal at a first sample rate and has delay blocks each providing an output and receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock. The outputs are multiplied by corresponding filter tap coefficients. Each filter tap coefficient is spaced by a first integer Y. The adder circuit receives and sums the tap outputs to provide an output signal. The selector iteratively shifts the coefficients by a second integer Z. The output of each delay block is multiplied by corresponding shifted filter tap coefficients. The delay blocks are inhibited from receiving another input sample during the plurality of clock cycles. The output signal has a second sample rate at the integer sub-multiple frequency of the clock.

摘要翻译： 包括延迟线，乘法器电路，加法器电路和选择器的无线收发机中的分数速率转换滤波器。 延迟线以第一采样率接收数字输入信号，并且具有延迟块，每个延迟块提供输出并接收在时钟的整数次多重频率的多个时钟周期中门控的采样。 输出乘以相应的滤波器抽头系数。 每个滤波器抽头系数由第一个整数Y隔开。加法器电路接收抽头输出并对其提供输出信号。 选择器将系数迭代地移位第二整数Z.每个延迟块的输出乘以相应的移位滤波器抽头系数。 在多个时钟周期期间，延迟块被禁止接收另一输入采样。 输出信号在时钟的整数子倍频率处具有第二采样率。

公开(公告)号：US08654662B2

公开(公告)日：2014-02-18

申请号：US12808070

申请日：2008-12-11

申请人： Steve Allpress ,  Laolu Lijofi ,  Donal Price

发明人： Steve Allpress ,  Laolu Lijofi ,  Donal Price

IPC分类号： H04J3/14

CPC分类号： H04W72/02 ,  H04W24/00

摘要： There is disclosed a method of determining one or more candidate frequencies for a carrier signal in a received signal, which method comprises: generating a narrowband spectrum of the received signal; detecting one or more peaks in the narrowband spectrum; generating a candidate frequency list, each frequency at which a peak occurs being included in the candidate frequency list. The method further comprises: removing the detected one or more peaks from the narrowband spectrum to generate a modified narrowband spectrum; detecting one or more further peaks in the modified narrowband spectrum; and modifying the candidate frequency list in dependence on the one or more further peaks.

摘要翻译： 公开了一种确定接收信号中载波信号的一个或多个候选频率的方法，该方法包括：产生接收信号的窄带频谱; 检测窄带谱中的一个或多个峰; 生成候选频率列表，发生峰值的每个频率被包括在候选频率列表中。 所述方法还包括：从所述窄带频谱中去除所检测到的一个或多个峰值以产生经修改的窄带频谱; 检测修改的窄带频谱中的一个或多个另外的峰; 以及根据一个或多个另外的峰值来修改候选频率列表。

公开(公告)号：US08484442B2

公开(公告)日：2013-07-09

申请号：US12964525

申请日：2010-12-09

申请人： Simon Knowles

发明人： Simon Knowles

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3891

摘要： A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a length of 21 bits. The decode unit detects that the instruction packet comprises the three control instructions. The control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet. The detection uses an identification bit in the instruction packet.

摘要翻译： 计算机处理器包括解码单元和处理通道。 解码单元从存储器解码指令包流，每个指令包包括多个指令。 处理通道包括多个功能单元并可操作以执行控制处理操作。 解码单元可操作以接收和解码64比特长度的指令分组，并且检测指令分组是否定义了每个具有21比特长度的三个控制指令。 解码单元检测到指令包包括三个控制指令。 控制指令以其出现在指令包中的顺序提供给处理通道以执行。 检测使用指令包中的标识位。

公开(公告)号：US08446935B2

公开(公告)日：2013-05-21

申请号：US13062611

申请日：2009-09-08

申请人： Hamid Safiri

发明人： Hamid Safiri

IPC分类号： H04B1/38

CPC分类号： H03H17/0685 ,  H03K5/159

摘要： A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal.

摘要翻译： 一种用于分数转换采样率的方法和系统。 通过对具有第一采样率的第一整数因子的输入信号进行上采样，去除由上转换处理产生的混叠，然后将中间信号下采样第二整数因子来提供收发器的发射路径的分数速率转换 最终信号具有第二采样率。 选择第一因子和第二因子以获得作为输入信号的采样率的一部分的期望输出采样率。

公开(公告)号：US20120300765A1

公开(公告)日：2012-11-29

申请号：US13575005

申请日：2011-01-27

申请人： Carlo Luschi ,  Simon Nicholas Walker

发明人： Carlo Luschi ,  Simon Nicholas Walker

IPC分类号： H04B7/216

CPC分类号： H04B1/707 ,  H04B2201/70702 ,  H04B2201/7071 ,  H04J11/005 ,  H04L2025/03726

摘要： A method, receiver and program for processing a signal received using a wireless communication channel by a receiver in a wireless cellular network. The method comprises: receiving signal samples of a signal to be processed from a serving cell; identifying a set of dominant interfering cells generating an interfering signal above a level; using the number of cells in the set to select an interference scenario; and using the selected interference scenario and at least one parameter related to the serving cell and the interfering cells to select a processing function for processing the signal.

摘要翻译： 一种用于处理由无线蜂窝网络中的接收机使用无线通信信道接收的信号的方法，接收机和程序。 该方法包括：从服务小区接收待处理信号的信号样本; 识别在一个电平以上产生干扰信号的一组主导干扰小区; 使用集合中的小区数来选择干扰场景; 以及使用所选择的干扰场景和与所述服务小区和所述干扰小区相关的至少一个参数来选择用于处理所述信号的处理功能。

公开(公告)号：US20120269307A1

公开(公告)日：2012-10-25

申请号：US13089808

申请日：2011-04-19

申请人： Mehmet T. Ozgun ,  Essam Atalla

发明人： Mehmet T. Ozgun ,  Essam Atalla

IPC分类号： H04L25/08 ,  H04B1/10

CPC分类号： H04B1/1036

摘要： Circuitry and a method for use in a radio frequency receiver for processing a radio frequency signal are provided. The circuitry comprises a mixer arranged to receive the radio frequency signal and down-convert the received radio frequency signal to a lower frequency. The received radio frequency signal has an interference component and the interference component in the down-converted signal is within an interference frequency range. The circuitry also comprises an LC based notch filter arranged to receive the down-converted signal from the mixer, filter the down-converted signal, and output the filtered signal for processing by a baseband processing block. The LC based notch filter has a notch centered within said interference frequency range, such that the LC based notch filter is arranged to attenuate the interference component in the down-converted signal.

摘要翻译： 提供了用于射频接收机中用于处理射频信号的电路和方法。 该电路包括一个混频器，被配置为接收射频信号并将接收到的射频信号下变频到较低的频率。 所接收的射频信号具有干扰分量，并且下变频信号中的干扰分量在干扰频率范围内。 该电路还包括基于LC的陷波滤波器，其布置成从混频器接收经下变频的信号，滤波下变频信号，并输出滤波后的信号以进行基带处理模块的处理。 基于LC的陷波滤波器具有以所述干扰频率范围为中心的陷波，使得基于LC的陷波滤波器被布置成衰减下变频信号中的干扰分量。

公开(公告)号：US20120256613A1

公开(公告)日：2012-10-11

申请号：US13081239

申请日：2011-04-06

申请人： Abdellatif Bellaouar ,  Arul Balasubramaniyan ,  Solti Peng

发明人： Abdellatif Bellaouar ,  Arul Balasubramaniyan ,  Solti Peng

IPC分类号： G05F3/02

CPC分类号： H04B15/06

摘要： A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor.

摘要翻译： 用于诸如压控振荡器（VCO）的功能电路的电源噪声抑制电路。 电源噪声抑制电路包括连接到电压源的隔离晶体管，用于在整个频率范围内提供基本上没有噪声的输出电流和电压。 电流源，二极管连接的参考晶体管，其电阻装置连接在其栅极和漏极端子之间，并且串联连接在电压源和地之间的虚拟电路产生施加到隔离晶体管的栅极的偏置电压。 虚拟电路模拟功能电路的DC特性，使得输出电流跟踪过程和温度变化。 隔离晶体管和参考晶体管可以具有负阈值电压，并且该电路可以包括用于从参考晶体管和隔离晶体管的栅极引出电流的放电装置。