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公开(公告)号：US20100029228A1
公开(公告)日：2010-02-04
申请号：US12520518
申请日：2007-12-20
申请人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
发明人： Alan Holden , Hamid Safiri , Michel J.G.J.P. Frechette , Sherif H.K. Embabi , Abdellatif Bellaouar , Stephen Arnold Devison , Tajinder Manku
IPC分类号： H04B1/04
CPC分类号： H03G3/3047
摘要： A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.
摘要翻译： 一种用于射频（RF）电路的发射路径的功率斜坡电路。 功率斜坡电路包括并联的晶体管，用作对数电阻衰减器，用于调节到发射路径中的混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并被依次关闭，以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联的晶体管。
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2.发明申请METHOD AND DEVICE FOR SENDING SIGNALS BETWEEN A RADIO FREQUENCY CIRCUIT AND A BASEBAND CIRCUIT 有权用于在无线电频率电路和基带电路之间发送信号的方法和装置公开(公告)号：US20140051365A1
公开(公告)日：2014-02-20
申请号：US13640079
申请日：2011-04-08
申请人： Abdellatif Bellaouar , Steve Felix , Hamid Safiri
发明人： Abdellatif Bellaouar , Steve Felix , Hamid Safiri
IPC分类号： H04B1/40
摘要： A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal. The data signal and the clock signal can then be sent between the radio frequency circuit and the baseband circuit using the selected clock frequency Fc.
摘要翻译： 提供一种方法，装置和计算机程序产品，用于在设备的射频电路和设备的基带电路之间发送数据信号和时钟信号，该射频电路被配置用于发送和接收 射频信号，其中时钟信号具有时钟频率Fc。 该方法包括选择时钟频率Fc为全球移动通信系统（GSM）标准的0.270833MHz符号率的合理倍数，以及宽带码分多址（WCDMA）的3.84MHz码片速率的有理倍数， 接口。 选择时钟频率Fc，使得可以使用38.4MHz或19.2MHz参考时钟信号，非分数锁相环时钟乘法器和输出分频器来产生时钟信号，而不必先分频参考时钟信号。 然后可以使用所选择的时钟频率Fc在数字信号和时钟信号之间在射频电路和基带电路之间发送。
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3.发明授权Method and device for sending signals between a radio frequency circuit and a baseband circuit 有权用于在射频电路和基带电路之间发送信号的方法和装置公开(公告)号：US09026069B2
公开(公告)日：2015-05-05
申请号：US13640079
申请日：2011-04-08
申请人： Abdellatif Bellaouar , Steve Felix , Hamid Safiri
发明人： Abdellatif Bellaouar , Steve Felix , Hamid Safiri
摘要： A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal. The data signal and the clock signal can then be sent between the radio frequency circuit and the baseband circuit using the selected clock frequency Fc.
摘要翻译： 提供一种方法，装置和计算机程序产品，用于在设备的射频电路和设备的基带电路之间发送数据信号和时钟信号，该射频电路被配置用于发送和接收 射频信号，其中时钟信号具有时钟频率Fc。 该方法包括选择时钟频率Fc为全球移动通信系统（GSM）标准的0.270833MHz符号率的合理倍数，以及宽带码分多址（WCDMA）的3.84MHz码片速率的有理倍数， 接口。 选择时钟频率Fc，使得可以使用38.4MHz或19.2MHz参考时钟信号，非分数锁相环时钟乘法器和输出分频器来产生时钟信号，而不必先分频参考时钟信号。 然后可以使用所选择的时钟频率Fc在数字信号和时钟信号之间在射频电路和基带电路之间发送。
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公开(公告)号：US08446935B2
公开(公告)日：2013-05-21
申请号：US13062611
申请日：2009-09-08
申请人： Hamid Safiri
发明人： Hamid Safiri
IPC分类号： H04B1/38
CPC分类号： H03H17/0685 , H03K5/159
摘要： A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal.
摘要翻译： 一种用于分数转换采样率的方法和系统。 通过对具有第一采样率的第一整数因子的输入信号进行上采样，去除由上转换处理产生的混叠，然后将中间信号下采样第二整数因子来提供收发器的发射路径的分数速率转换 最终信号具有第二采样率。 选择第一因子和第二因子以获得作为输入信号的采样率的一部分的期望输出采样率。
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公开(公告)号：US08836434B2
公开(公告)日：2014-09-16
申请号：US13062583
申请日：2009-09-08
CPC分类号： H03L7/093 , H03C3/0925 , H03C3/0933 , H03C3/0991 , H03L7/1976
摘要： A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
摘要翻译： 具有自动校准系统的数字频率合成器。 数字频率合成器通过启动粗略调谐操作来校准，以快速达到接近期望最终频率的初步频率。 然后根据初步频率执行校准程序，以调整频率合成器中的增益。 该测试涉及将一个或多个测试信号应用于频率合成器并测量在频率合成器中产生的信号。 该测量信号对应于初始频率处电路的增益响应。 当预期增益是已知的时，使用相对于测量信号的增益的任何差异来调整频率合成器的电路中的增益，使得实际增益基本上与预期的增益相匹配。
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公开(公告)号：US20110164663A1
公开(公告)日：2011-07-07
申请号：US13062611
申请日：2009-09-08
申请人： Hamid Safiri
发明人： Hamid Safiri
IPC分类号： H04B1/38
CPC分类号： H03H17/0685 , H03K5/159
摘要： A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal.
摘要翻译： 一种用于分数转换采样率的方法和系统。 通过对具有第一采样率的第一整数因子的输入信号进行上采样，去除由上转换处理产生的混叠，然后将中间信号下采样第二整数因子来提供收发器的发射路径的分数速率转换 最终信号具有第二采样率。 选择第一因子和第二因子以获得作为输入信号的采样率的一部分的期望输出采样率。
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公开(公告)号：US20110163815A1
公开(公告)日：2011-07-07
申请号：US13062583
申请日：2009-09-08
CPC分类号： H03L7/093 , H03C3/0925 , H03C3/0933 , H03C3/0991 , H03L7/1976
摘要： A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.
摘要翻译： 具有自动校准系统的数字频率合成器。 数字频率合成器通过启动粗略调谐操作来校准，以快速达到接近期望最终频率的初步频率。 然后根据初步频率执行校准程序，以调整频率合成器中的增益。 该测试涉及将一个或多个测试信号应用于频率合成器并测量在频率合成器中产生的信号。 该测量信号对应于初始频率处电路的增益响应。 当预期增益是已知的时，使用相对于测量信号的增益的任何差异来调整频率合成器的电路中的增益，使得实际增益基本上与预期的增益相匹配。
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