Diversion valve fluid coupling
    61.
    发明授权
    Diversion valve fluid coupling 有权
    引流阀流体联轴器

    公开(公告)号:US07213616B2

    公开(公告)日:2007-05-08

    申请号:US10916003

    申请日:2004-08-11

    Abstract: A diversion valve fluid coupling, permitting alternate flows in first and second operating positions, including a valve housing with inlet, first and second outlet ports; a quick disconnect coupling attached to the second outlet port and a seal interposed therebetween; a movable diverter valve assembly, having interconnected actuating and opposing valves; the actuating valve, in the first operating position, having a first sealing engagement with the seal; the opposing valve, in the second operating position, having a second sealing engagement with a first outlet port; a biasing member, biasing the diverter valve into the first sealing engagement, blocking the second outlet port while permitting flow to the first outlet port; and, for the second operating position, a nipple member, removably mating with the quick disconnect coupling and translating the diverter valve into the second sealing engagement, blocking the first outlet port while permitting flow into the second outlet port.

    Abstract translation: 分流阀流体联接器,允许在第一和第二操作位置中的交替流动,包括具有入口,第一和第二出口的阀壳; 连接到第二出口的快速断开联接件和插在其间的密封件; 可移动分流阀组件,具有互连的致动和相对的阀门; 所述致动阀在所述第一操作位置具有与所述密封件的第一密封接合; 所述相对阀在所述第二操作位置具有与第一出口端口的第二密封接合; 偏压构件,其将所述分流阀偏压到所述第一密封接合中,阻止所述第二出口同时允许流入所述第一出口; 并且对于第二操作位置,乳头构件可移除地与快速切断联接件配合并将分流阀平移到第二密封接合中,在允许流入第二出口端口的同时阻止第一出口。

    Pulsed thermistor sensor
    62.
    发明申请
    Pulsed thermistor sensor 有权
    脉冲热敏电阻传感器

    公开(公告)号:US20050092078A1

    公开(公告)日:2005-05-05

    申请号:US10974494

    申请日:2004-10-27

    CPC classification number: G01F1/6986 G01F1/69 G01F1/696

    Abstract: A thermistor is pulsed with energy, and a time constant of decay of temperature is calculated based on measured resistance of the thermistor over a number of known intervals. The time constant is representative of the mass air flow. The ambient air temperature may be found without waiting for the thermistor to reach the ambient air temperature.

    Abstract translation: 热敏电阻用能量脉冲,并且基于在多个已知间隔内测得的热敏电阻的电阻来计算温度衰减的时间常数。 时间常数代表大气流量。 可以在不等待热敏电阻达到环境空气温度的情况下找到环境空气温度。

    All-optical processing in communications systems
    64.
    发明授权
    All-optical processing in communications systems 失效
    通信系统中的全光学处理

    公开(公告)号:US5953138A

    公开(公告)日:1999-09-14

    申请号:US817347

    申请日:1997-04-16

    CPC classification number: H04B10/25077 H04J14/02 H04J14/0223

    Abstract: An all-optical processing system coverts or interfaces optical signals from a wavelength division multiplexed (WDM) form to an optical time divisional multiplexed (OTDM) form. The initial WDM signal typically comprises a non-return to zero (NRZ) signalling format. The system includes a plurality of NRZ data modulated, cw optical WDM channels which are cross-phase modulated, and thus are spectrally broadened, in an optical non-linear element, by a strong clock pulse signal. The resultant signal comprises an RZ representation of the original NRZ signal. The RZ signal is temporally shifted by a dispersive element which temporally shifts each wavelength channel by a predetermined amount, to produce a wavelength-interleaved OTDM signal. The signal is then wavelength converted by cross-phase modulation with a cw control beam in a second non-linear optical element to provide a single wavelength OTDM signal.

    Abstract translation: PCT No.PCT / GB95 / 02471 Sec。 371日期1997年04月16日 102(e)日期1997年4月16日PCT 1995年10月19日PCT PCT。 第WO96 / 13104号公报 日期:1996年5月2日全光处理系统将从波分复用(WDM)形式到光时分多路复用(OTDM)形式的光信号覆盖或接口。 初始WDM信号通常包括不归零(NRZ)信令格式。 该系统包括通过强时钟脉冲信号在光学非线性元件中进行交叉相位调制并因此被光谱扩展的多个NRZ数据调制的cw光WDM信道。 所得信号包括原始NRZ信号的RZ表示。 RZ信号由时间上偏移每个波长信道预定量的色散元件暂时移位,以产生波长交错的OTDM信号。 然后,通过在第二非线性光学元件中的cw控制光束通过交叉相位调制对信号进行波长转换,以提供单个波长OTDM信号。

    System for restoration of communications networks

    公开(公告)号:US5706276A

    公开(公告)日:1998-01-06

    申请号:US435030

    申请日:1995-05-04

    Abstract: Difficulties with prior disrupted communications restoration systems are overcome by employing for each node of a communications network a restoration processor in which predetermined functions of the restoration process are managed by respective ones of a plurality of manager modules. The manager modules are arranged to be directly interconnected only with a so-called restoration manager that coordinates the operations of the modules and provides for their interconnection needs. In a preferred embodiment, four manager modules, a) a user interface manager module, b) a digital cross-connect system (DCS) manager module, c) a distributed communications manager module and d) a core algorithm manager module, are interconnected and coordinated by the restoration manager. Additional robustness to the restoration process is provided by way of enhancements to the functionality of the core algorithm manager module. These enhancements include: a) improved glare processing (resolution of contention for a particular resource), b) "broadcast" of takedown messages, c) elimination of the need for time-outs during automatic restoration, d) a "peek ahead" routine that immediately takes down a needed resource that is already on a list to be taken down, e) use of a "minimax factor" and f) a "quick fix" technique for use in cases of limited failure of circuits between two nodes. The restoration process can also be cascaded so that it sequentially restores one level at a time, the levels being defined by the hierarchy of digital transmission rates employed in the network.

    Apparatus and method for sharing first-in first-out memory space between
two streams of data
    66.
    发明授权
    Apparatus and method for sharing first-in first-out memory space between two streams of data 失效
    用于在两个数据流之间共享先进先出存储器空间的装置和方法

    公开(公告)号:US5696940A

    公开(公告)日:1997-12-09

    申请号:US536649

    申请日:1995-09-29

    CPC classification number: G06F13/4059

    Abstract: A random access memory (RAM) device that allocates memory cells to first-in first-out (FIFO) memory. The RAM device has an array of addressable memory cells that are selected by row and column decoders. The memory cells and decoders have dual read and write lines that allow simultaneous read and write operations on the memory cells. The memory cells can store data from at least two data streams including, by way of example, a stream of U data and a stream of V data from an input device such as a YUV video processor. The RAM device includes a control circuit which generates separate read and write pointers for the U and V data. The control circuit also generates separate U and V minimum and almost full trigger pointers. Data is written into the memory cells until a write pointer reaches either a minimum trigger pointer or an almost full trigger pointer. When a write pointer exceeds a minimum or almost full trigger pointer, the control circuit requests that data be read from the memory cells so that morse data can be written into the memory cells. The minimum and almost full trigger pointers are programmable so that the memory space allocated to each data stream is dynamically variable.

    Abstract translation: 将存储器单元分配给先进先出(FIFO)存储器的随机存取存储器(RAM)设备。 RAM设备具有由行和列解码器选择的可寻址存储器单元的阵列。 存储单元和解码器具有双重读和写行,允许对存储单元进行同时的读和写操作。 存储器单元可以存储来自至少两个数据流的数据,包括例如来自诸如YUV视频处理器的输入设备的U数据流和V数据流。 RAM装置包括一个控制电路,为U和V数据产生单独的读和写指针。 控制电路还生成单独的U和V最小和几乎全触发指针。 将数据写入存储单元,直到写指针达到最小触发指针或几乎完全的触发指针。 当写指针超过最小或几乎全触发指针时,控制电路请求从存储单元读取数据,以便将莫尔斯数据写入存储单元。 最小和几乎完全的触发指针是可编程的,使得分配给每个数据流的存储器空间是动态变量的。

    State machine operating in multiple parallel phase and method thereof
    67.
    发明授权
    State machine operating in multiple parallel phase and method thereof 失效
    国家机器在多个并行阶段运行及其方法

    公开(公告)号:US5394557A

    公开(公告)日:1995-02-28

    申请号:US998795

    申请日:1992-12-30

    Applicant: David Ellis

    Inventor: David Ellis

    CPC classification number: G06F1/10

    Abstract: A state machine circuit comprising a first phased circuit clocked by a first phased clock and a second phased circuit clocked by a second phased clock. The first phased circuit includes a first input register which sequences and stores at least one input signal; a first combinatorial logic network which produces a number of output control signals wherein each of the control signals has a next state signal and a jump index signal; a first multiplexer to select one of the output control signals; and a first output register which sequences and stores the selected output control signal and also (i) feeds back the next state signal into the first combinatorial logic network, (ii) outputs the jump index into a second selector, and (iii) outputs the selected control signal, absent the next state signal and the jump index, to a device. The second phased circuit is identical in structure and function to the first phased circuit and includes a second input register, a second combinatorial logic network, a second multiplexer and a second output register.

    Abstract translation: 一种状态机电路,包括由第一相位时钟定时的第一相控电路和由第二相位时钟计时的第二相电路。 第一相位电路包括第一输入寄存器,其对至少一个输入信号进行序列和存储; 产生多个输出控制信号的第一组合逻辑网络,其中每个控制信号具有下一状态信号和跳转索引信号; 第一多路复用器,用于选择输出控制信号之一; 以及第一输出寄存器,其对所选择的输出控制信号进行排序和存储,并且(i)将下一状态信号反馈到第一组合逻辑网络中,(ii)将跳转索引输出到第二选择器,并且(iii) 选择的控制信号,不存在下一个状态信号和跳转指标。 第二相位电路的结构和功能与第一相位电路相同,并且包括第二输入寄存器,第二组合逻辑网络,第二多路复用器和第二输出寄存器。

    Method and apparatus for deskewing/resynchronizing data slices with
variable skews
    68.
    发明授权
    Method and apparatus for deskewing/resynchronizing data slices with variable skews 失效
    用于使数据切片与变量偏移进行偏斜/重新同步的方法和装置

    公开(公告)号:US5392318A

    公开(公告)日:1995-02-21

    申请号:US40902

    申请日:1993-03-31

    CPC classification number: G06F5/065

    Abstract: Each data sending high speed circuit generating and sending a stream of data slices and a stream of clock pulses is provided with a sync pulse generation circuit for synchronously generating and sending an accompanying stream of periodic sync pulses. The various streams of data slices, clock pulses, and periodic sync pulses incur varying amount of delays as they travel from the data sending high speed circuits to a data acquisition circuit. The data acquisition high speed circuit is provided with a plurality of circular buffer chains of appropriate length for independently buffering the skewed data slices until all corresponding data slices have been received and buffered, and then concurrently reading the buffered corresponding data slices out of the circular buffer chains. The data acquisition high speed circuit is also provided with a plurality of corresponding independent write address generators and a common read address generator for generating the independent write buffer addressed and the synchronized read buffer addresses using the data clocks and the periodic sync pulses. As a result, the skewed data slices are deskewed or resynchronized as they are read out of the circular buffer chain.

    Abstract translation: 每个发送高速电路的数据发送和发送数据片段流和时钟脉冲流都提供有同步脉冲产生电路,用于同步产生和发送周期性同步脉冲的伴随流。 数据片,时钟脉冲和周期性同步脉冲的各种流在从发送高速电路的数据传输到数据采集电路时会引起不同的延迟量。 数据采集​​高速电路具有适当长度的多个循环缓冲链,用于独立地缓存偏斜数据片,直到所有对应的数据片已被接收和缓存,然后从循环缓冲器中同时读取缓冲的相应数据片 链条 数据采集​​高速电路还具有多个对应的独立写入地址发生器和用于使用数据时钟和周期性同步脉冲来产生独立写缓冲器寻址的同步读缓冲器地址的公共读地址发生器。 因此,倾斜的数据切片在从循环缓冲区链​​中读出时进行了偏斜校正或重新同步。

    Method and means for making an explosive in the form of an emulsion
    69.
    发明授权
    Method and means for making an explosive in the form of an emulsion 失效
    用于制造乳液形式的爆炸物的方法和装置

    公开(公告)号:US4491489A

    公开(公告)日:1985-01-01

    申请号:US539405

    申请日:1983-10-06

    CPC classification number: C06B47/145 C06B21/00

    Abstract: A method of making an explosive in the form of an emulsion, which includes two stages being a first stage comprising directing a plurality of 0.5 to 5 mm diameter jets of the discontinuous phase into the continuous phase, in the presence of an emulsifier, and feeding the continuous phase containing the discontinuous phase through a static mixer to form a relatively coarse, fuel-rich emulsion; and a second stage comprising directing a plurality of 0.5 to 5 mm diameter jets of the discontinuous phase into the continuous phase of said coarse emulsion, and feeding the coarse emulsion with the added discontinuous phase through two further static mixers arranged in series. The invention further extends to an apparatus for performing the method of the invention.

    Abstract translation: 一种以乳液形式制造爆炸物的方法,其包括两个阶段,该阶段是第一阶段,包括在乳化剂存在下将不连续相的多个0.5至5mm直径的射流引入连续相,并且进料 连续相通过静态混合器包含不连续相,以形成相对粗大的富燃料乳液; 以及第二阶段,包括将不连续相的多个0.5至5mm直径的射流引导到所述粗乳液的连续相中,并且通过串联布置的两个另外的静态混合器将具有所述不连续相的粗乳液进料。 本发明进一步延伸到用于执行本发明的方法的装置。

Patent Agency Ranking