Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread
    62.
    发明授权
    Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread 失效
    通过索引到每个线程的目标寄存器历史记录表来指定指令代码中较少位的操作数

    公开(公告)号:US07814299B2

    公开(公告)日:2010-10-12

    申请号:US12274560

    申请日:2008-11-20

    CPC classification number: G06F9/30098 G06F9/3016 G06F9/3832

    Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.

    Abstract translation: 一种电路布置和方法支持指令目标历史的寄存器地址索引,由此由指令使用的寄存器地址使用先前目标寄存器地址的目标历史表和由目标历史表中的索引值提供的索引进行解码 指示。 指令可以包括标识先前使用的寄存器地址的至少一个索引值。 在执行指令期间,从指令中检索索引,然后使用索引从目标历史表中检索一个寄存器地址。

    Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management
    64.
    发明申请
    Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management 审中-公开
    加工单元结合发行费率预测热管理

    公开(公告)号:US20090182986A1

    公开(公告)日:2009-07-16

    申请号:US12015174

    申请日:2008-01-16

    Abstract: A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are issued to one or more execution units in the processing unit, and selectively delays the issuance of subsequent instructions to the execution unit(s) based upon the tracked issue rate to predictively control the thermal output of the integrated circuit.

    Abstract translation: 电路布置和方法利用微处理器或其他集成电路中的基于问题率的预测热管理技术,该微处理器或其他集成电路跟踪指令被发送到处理单元中的一个或多个执行单元的速率,并且选择性地延迟后续指令的发布 基于跟踪的发布速率来预测地控制集成电路的热输出的执行单元。

    Method and Apparatus for an Area Efficient Transcendental Estimate Algorithm
    65.
    发明申请
    Method and Apparatus for an Area Efficient Transcendental Estimate Algorithm 失效
    用于区域有效超验估计算法的方法和装置

    公开(公告)号:US20090070398A1

    公开(公告)日:2009-03-12

    申请号:US11851658

    申请日:2007-09-07

    CPC classification number: G06F7/548

    Abstract: A method, computer-readable medium, and an apparatus for generating a transcendental value. The method includes receiving an input containing an input value and an opcode and determining whether the opcode corresponds to a trigonometric operation or a power-of-two operation. The method also includes calculating a fractional value and an integer value from the input value, generating the transcendental value based on the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value, and providing the transcendental value in response to the request. In this fashion, the same circuit area may be used to carry out both trigonometric and power-of-two calculations, leading to greater circuit area savings and performance advantages while not sacrificing significant accuracy.

    Abstract translation: 一种用于产生超验值的方法,计算机可读介质和装置。 该方法包括接收包含输入值和操作码的输入,并确定操作码是否对应于三角运算或二进制运算。 该方法还包括从输入值计算分数值和整数值,通过将分数值的至少一部分与通过移动部分产生的移位分数值中的至少一个相加而基于分数值生成超越值 的分数值和恒定值,并且响应于该请求提供超验值。 以这种方式,可以使用相同的电路面积来执行三角和二次幂计算,导致更大的电路面积节省和性能优点,而不牺牲显着的精度。

    Operand Multiplexor Control Modifier Instruction in a Fine Grain Multithreaded Vector Microprocessor
    66.
    发明申请
    Operand Multiplexor Control Modifier Instruction in a Fine Grain Multithreaded Vector Microprocessor 失效
    精细多线程向量微处理器中的操作数多路复用器控制修改器指令

    公开(公告)号:US20080122854A1

    公开(公告)日:2008-05-29

    申请号:US11564072

    申请日:2006-11-28

    CPC classification number: G06T1/20

    Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

    Abstract translation: 本发明通常涉及图像处理领域,更具体地涉及用于处理图像的指令集。 矢量处理可以包括在执行向量操作之前在一个或多个源寄存器中重新排列向量操作数。 通常,通过发出需要临时寄存器过度使用的多个置换指令来完成源寄存器中操作数的重新排列。 此外,置换指令可能导致在流水线中执行的指令之间的相关性,从而不利地影响性能。 本发明的实施例提供了一种在寄存器文件和向量单元之间的复用水平,其允许在将操作数提供给向量单元之前重新排列源寄存器中的向量操作数,从而避免了对置换指令的需要。

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