Tree insertion depth adjustment based on view frustum and distance culling
    1.
    发明授权
    Tree insertion depth adjustment based on view frustum and distance culling 有权
    基于视锥截面和距离剔除的树插入深度调整

    公开(公告)号:US08593459B2

    公开(公告)日:2013-11-26

    申请号:US13476876

    申请日:2012-05-21

    CPC分类号: G06T15/06 G06T17/005

    摘要: A computer-implemented method includes initializing a driver associated with an input/output adapter in response to receiving an initialize driver request from a client application. The computer-implemented method includes initializing the input/output adapter to enable adapter capabilities of the input/output adapter to be determined. The computer-implemented method also includes determining the adapter capabilities of the input/output adapter. The computer-implemented method further includes determining slot capabilities of a slot associated with the input/output adapter. The computer-implemented method also includes setting configurable capabilities of the input/output adapter based on the adapter capabilities and the slot capabilities.

    摘要翻译: 计算机实现的方法包括初始化与输入/输出适配器相关联的驱动程序以响应于从客户端应用程序接收到初始化驱动程序请求。 计算机实现的方法包括初始化输入/输出适配器以确定输入/输出适配器的适配器能力。 计算机实现的方法还包括确定输入/输出适配器的适配器能力。 计算机实现的方法还包括确定与输入/输出适配器相关联的时隙的时隙能力。 计算机实现的方法还包括基于适配器能力和时隙能力来设置输入/输出适配器的可配置功能。

    Implied storage operation decode using redundant target address detection
    2.
    发明授权
    Implied storage operation decode using redundant target address detection 有权
    隐藏存储操作使用冗余目标地址检测进行解码

    公开(公告)号:US08255674B2

    公开(公告)日:2012-08-28

    申请号:US12360975

    申请日:2009-01-28

    IPC分类号: G06F9/312

    摘要: A logic arrangement and method to support implied storage operation decode uses redundant target address detection, whereby target addresses of previous instructions are compared with the target address of the current instruction, and if equal, and the target addresses of previous instructions are not used as sources, the current instruction is decoded as a store instruction. This allows a redundant operation in an instruction set architecture to be redefined as a store instruction, freeing up opcodes normally used for store instructions to be used for other instructions.

    摘要翻译: 支持隐含存储操作解码的逻辑布置和方法使用冗余目标地址检测,由此将先前指令的目标地址与当前指令的目标地址进行比较,如果相等,并且先前指令的目标地址不被用作源 ,当前指令被解码为存储指令。 这允许将指令集架构中的冗余操作重新定义为存储指令,释放通常用于存储指令的操作码以用于其他指令。

    Anisotropic texture filtering with texture data prefetching
    3.
    发明授权
    Anisotropic texture filtering with texture data prefetching 有权
    具有纹理数据预取的各向异性纹理过滤

    公开(公告)号:US08217953B2

    公开(公告)日:2012-07-10

    申请号:US12110045

    申请日:2008-04-25

    IPC分类号: G09G5/00

    CPC分类号: G06T15/04 G06T2200/12

    摘要: A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.

    摘要翻译: 电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。 特别地,可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据,其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离 在各向异性过滤算法中使用各向异性。

    Processing unit incorporating multirate execution unit
    4.
    发明授权
    Processing unit incorporating multirate execution unit 失效
    包含多速率执行单元的处理单元

    公开(公告)号:US07945764B2

    公开(公告)日:2011-05-17

    申请号:US11972746

    申请日:2008-01-11

    IPC分类号: G06F9/30

    摘要: A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the execution unit can be clocked at a rate that is faster than the clock rate for the multithreaded issue unit, and in applications where a lower power profile is desired, the execution unit can be throttled back to a slower rate to reduce the power consumption of the execution unit. When the execution unit is clocked at a faster rate than the multithreaded issue unit, the issue unit is permitted to issue more instructions per cycle than when the execution unit is throttled to the slower rate to increase overall instruction throughput.

    摘要翻译: 多速率执行单元能够以多种模式操作,其中执行单元能够以相对于多线程发布单元的多个不同速率进行计时,使得在需要最大性能的应用中,执行单元可被计时 以比多线程发布单元的时钟速率快的速率,以及在需要较低功率配置的应用中,执行单元可以被限制回到较慢的速率以降低执行单元的功耗。 当执行单元以比多线程发布单元更快的速度进行计时时,允许发布单元每循环发出更多指令,而不是执行单元被限制到较慢的速率以增加总体指令吞吐量。

    Dual independent and shared resource vector execution units with shared register file
    5.
    发明授权
    Dual independent and shared resource vector execution units with shared register file 有权
    具有共享寄存器文件的双独立和共享资源向量执行单元

    公开(公告)号:US07926009B2

    公开(公告)日:2011-04-12

    申请号:US11924980

    申请日:2007-10-26

    IPC分类号: G06F17/50

    摘要: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

    摘要翻译: 本发明通常涉及集成电路装置,更具体地涉及图像处理领域的方法,系统和设计结构,更具体地涉及用于支持图像处理的矢量单元。 描述了双向量单元实现,其中配置了两个向量单元从公共寄存器文件接收数据。 向量单元可以独立地并且同时处理指令。 此外,矢量单元可以适于执行标量运算,从而整合向量和标量处理。 矢量单元还可以被配置为共享资源以执行操作,例如交叉产品操作。

    Processing Unit Incorporating Instruction-Based Persistent Vector Multiplexer Control
    7.
    发明申请
    Processing Unit Incorporating Instruction-Based Persistent Vector Multiplexer Control 失效
    结合基于指令的持续矢量多路复用器控制的处理单元

    公开(公告)号:US20090228681A1

    公开(公告)日:2009-09-10

    申请号:US12045221

    申请日:2008-03-10

    IPC分类号: G06F9/30 G06F15/76

    摘要: Persistent vector multiplexer control is used in a vector-based execution unit to control the shuffling of words in operand vectors processed by the execution unit. In addition, a persistent swizzle instruction is defined in an instruction set for the vector-based execution unit and is used to cause state information to be persisted such that the operand vectors processed by subsequent vector instructions executed by the vector-based execution unit will be selectively shuffled using the persisted state information. As a result, when multiple vector instructions require a common custom word ordering for one or more operand vectors, a single persistent swizzle instruction may be used to select the desired custom word ordering for all of the vector instructions.

    摘要翻译: 持续矢量复用器控制在基于矢量的执行单元中用于控制由执行单元处理的操作数向量中的字的混洗。 此外,在用于基于向量的执行单元的指令集中定义持续转换指令,并且用于使状态信息被持久化,使得由基于向​​量的执行单元执行的后续向量指令处理的操作数向量将被 使用持久状态信息选择性地进行混洗。 因此,当多个向量指令需要一个或多个操作数向量的公共自定义单词排序时,可以使用单个持续旋转指令来选择所有向量指令的期望的定制单词排序。

    Method and Apparatus for Implementing a Multiple Operand Vector Floating Point Summation to Scalar Function
    8.
    发明申请
    Method and Apparatus for Implementing a Multiple Operand Vector Floating Point Summation to Scalar Function 失效
    用于实现多操作数向量浮点求和的标量函数的方法和装置

    公开(公告)号:US20090049113A1

    公开(公告)日:2009-02-19

    申请号:US11840277

    申请日:2007-08-17

    IPC分类号: G06F7/38

    摘要: Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a pair of operands in each processing lane of a vector unit. The arithmetic results generated in each processing lane of the vector unit may be transferred to a dot product unit. The dot product unit may compute an arithmetic result using the arithmetic result computed by each processing lane of the vector unit to generate an arithmetic result of more than two operands.

    摘要翻译: 本发明的实施例提供了用于执行多操作数指令的方法和装置。 执行多操作数指令包括​​计算向量单元的每个处理通道中的一对操作数的算术结果。 在矢量单元的每个处理车道中产生的算术结果可以被转移到点积单位。 点积单位可以使用由向量单位的每个处理车道计算的算术结果来计算算术结果,以生成超过两个操作数的算术结果。

    Method and Apparatus for Generating Trigonometric Results
    9.
    发明申请
    Method and Apparatus for Generating Trigonometric Results 失效
    用于产生三角测量结果的方法和装置

    公开(公告)号:US20080183783A1

    公开(公告)日:2008-07-31

    申请号:US11668040

    申请日:2007-01-29

    申请人: Matthew Ray Tubbs

    发明人: Matthew Ray Tubbs

    IPC分类号: G06F1/02 G06F7/548

    CPC分类号: G06F7/548

    摘要: A method, computer-readable medium, and apparatus for generating a trigonometric value. The method includes receiving a request to calculate a trigonometric value for an angle value and calculating a fractional value from the angle value. The fractional value corresponds to one of a first quadrant value, a second quadrant value, a third quadrant value, and a fourth quadrant value. The method also includes using the fractional value to determine whether to perform at least one of inverting the fractional value and negating the trigonometric value. The method further includes generating the trigonometric value from the fractional value by adding at least a portion of the fractional value with at least one of a shifted fractional value produced by shifting the portion of the fractional value and a constant value and providing the trigonometric value in response to the request.

    摘要翻译: 一种用于产生三角值的方法,计算机可读介质和装置。 该方法包括接收计算角度值的三角值并从角度值计算分数值的请求。 分数值对应于第一象限值,第二象限值,第三象限值和第四象限值中的一个。 该方法还包括使用分数值来确定是否执行反转小数值和否定三角值中的至少一个。 该方法还包括通过将分数值的至少一部分与通过移动分数值的一部分和恒定值而产生的移位分数值中的至少一个相加,从而产生三角值,并将三角值提供给 响应请求。

    LOW POWER DMA SNOOP AND SKIP
    10.
    发明申请
    LOW POWER DMA SNOOP AND SKIP 审中-公开
    低功耗DMA SNOOP和SKIP

    公开(公告)号:US20160180494A1

    公开(公告)日:2016-06-23

    申请号:US14574100

    申请日:2014-12-17

    IPC分类号: G06T1/60 G06T7/40

    摘要: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.

    摘要翻译: 描述了在从第一存储器(例如,DRAM)到第二存储器(例如,SRAM)的像素数据的数据传输期间使用直接存储器访问(DMA)引擎来预处理像素数据的方法。 像素数据可以从彩色相机或深度相机中得出,其中各个像素值不是8位的倍数。 在某些情况下,DMA引擎可以在将像素数据写入第二存储器之前对像素数据执行各种图像处理操作。 在一个实施例中,DMA引擎可以被配置为基于最小像素值阈值和最大像素值阈值来确定与像素数据相对应的一个或多个像素可能被无效或跳过,并且将像素跳过信息嵌入到未使用的位内 像素数据。