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    High-density low-power data retention power gating with double-gate devices
    61.
    发明申请
    High-density low-power data retention power gating with double-gate devices 有权
    具有双栅极器件的高密度低功耗数据保持功率门控

    公开(公告)号：US20060232321A1

    公开(公告)日：2006-10-19

    申请号：US11106913

    申请日：2005-04-15

    Applicant: Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

    Inventor： Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

    IPC: H03K17/687

    CPC classification number: H01L27/105 ,  G11C5/14 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/785 ,  H01L29/78648 ,  H03K3/356156

    Abstract: A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

    Abstract translation: 具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。 该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。 该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。 还提出了拟议方案的虚拟供应/地面反弹分析。

    High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs
    62.
    发明申请
    High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs 失效
    用于混合定向技术的高性能PFET接头，用于数字CMOS VLSI设计中的漏电减少

    公开(公告)号：US20060226493A1

    公开(公告)日：2006-10-12

    申请号：US11100883

    申请日：2005-04-07

    Applicant: Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

    Inventor： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

    IPC: H01L29/94

    CPC classification number: H03K19/0016 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    Abstract: Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG

    Abstract translation: 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG

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