公开(公告)号：US20190238758A1

公开(公告)日：2019-08-01

申请号：US16376479

申请日：2019-04-05

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US20190213006A1

公开(公告)日：2019-07-11

申请号：US16251887

申请日：2019-01-18

Applicant: Google LLC

Inventor： Artem Vasilyev ,  Jason Rupert Redgrave ,  Albert Meixner ,  Ofer Shacham

IPC: G06F9/30 ,  G06F7/57 ,  G06F15/80

CPC classification number: G06F9/3001 ,  G06F7/57 ,  G06F9/30014 ,  G06F15/80

Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.

公开(公告)号：US10334194B2

公开(公告)日：2019-06-25

申请号：US15946095

申请日：2018-04-05

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/225 ,  H04N5/374 ,  G06T1/20 ,  H04N5/341 ,  G06F5/01 ,  G06F12/02 ,  G06F17/16

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.