Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND
    61.
    发明授权
    Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND 有权
    深度字线沟槽,用于屏蔽相邻单元之间的交叉耦合,用于缩放NAND

    公开(公告)号:US07170786B2

    公开(公告)日:2007-01-30

    申请号:US11086648

    申请日:2005-03-21

    IPC分类号: G11C16/04

    CPC分类号: H01L27/11524 G11C16/0483

    摘要: A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

    摘要翻译: 具有字线或控制门的NAND闪速存储器结构,其提供对Yupin的屏蔽效应,并且通常来自经历具有显着的电位变化的编程操作的相邻串中的电位。

    Non-volatile memory cells utilizing substrate trenches
    65.
    发明授权
    Non-volatile memory cells utilizing substrate trenches 有权
    利用衬底沟槽的非易失性存储单元

    公开(公告)号:US07491999B2

    公开(公告)日:2009-02-17

    申请号:US11423121

    申请日:2006-06-08

    IPC分类号: H01L29/72

    摘要: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    摘要翻译: 描述了闪存EEPROM分离通道单元阵列的几个实施例,其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁,从而减小单元面积。 选择晶体管栅极形成为字线的一部分,并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中,在沿着一行的每隔一个浮置栅极之间形成沟槽,两个沟槽侧壁为相邻电池提供选择晶体管沟道,并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中,在沿着一排的每个浮置栅极之间形成沟槽,沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中,双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中,以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

    Non-Volatile Memory Cells Utilizing Substrate Trenches
    66.
    发明申请
    Non-Volatile Memory Cells Utilizing Substrate Trenches 有权
    非易失性记忆单元利用基底沟槽

    公开(公告)号:US20060227620A1

    公开(公告)日:2006-10-12

    申请号:US11423121

    申请日:2006-06-08

    IPC分类号: G11C11/34 G11C16/06

    摘要: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

    摘要翻译: 描述了闪存EEPROM分离通道单元阵列的几个实施例,其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁,从而减小单元面积。 选择晶体管栅极形成为字线的一部分,并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中,在沿着一行的每隔一个浮置栅极之间形成沟槽,两个沟槽侧壁为相邻电池提供选择晶体管沟道,并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中,在沿着一排的每个浮置栅极之间形成沟槽,沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中,双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中,以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

    Wireless audio output assembly for projectors
    67.
    发明申请
    Wireless audio output assembly for projectors 失效
    投影机的无线音频输出组件

    公开(公告)号:US20060132715A1

    公开(公告)日:2006-06-22

    申请号:US11014826

    申请日:2004-12-20

    IPC分类号: G03B31/00

    CPC分类号: G03B21/14 G03B21/54 G03B31/00

    摘要: The present invention discloses an improved wireless audio output assembly for projectors, which comprises a system unit having a projector circuit therein and a projector lens disposed on the exterior of the system unit, and the system unit has a card-type wireless audio output circuit installed therein and a wireless active speaker installed on the exterior of the system unit, so that a projector can be used as a standalone device without connecting to external cables to read data from a memory card, view video images, and read audio/video signals of an optical disk. The projector can be upgraded to the user's desired wireless audio output circuit by inserting various different cards for the expansion.

    摘要翻译: 本发明公开了一种用于投影机的改进的无线音频输出组件,其包括其中具有投影仪电路的系统单元和设置在系统单元的外部的投影仪透镜,并且系统单元具有安装在卡式无线音频输出电路 其中安装在系统单元的外部的无线主动扬声器,使得投影仪可以用作独立设备而不连接到外部电缆以从存储卡读取数据,观看视频图像和读取音频/视频信号 光盘。 投影机可以通过插入各种不同的扩展卡来升级到用户所需的无线音频输出电路。