公开(公告)号：US20060227620A1

公开(公告)日：2006-10-12

申请号：US11423121

申请日：2006-06-08

申请人： Eliyahou Harari ,  Jack Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

公开(公告)号：US07087951B2

公开(公告)日：2006-08-08

申请号：US10848242

申请日：2004-05-17

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

公开(公告)号：US06936887B2

公开(公告)日：2005-08-30

申请号：US09925134

申请日：2001-08-08

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

公开(公告)号：US07491999B2

公开(公告)日：2009-02-17

申请号：US11423121

申请日：2006-06-08

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： H01L29/72

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

公开(公告)号：US5654217A

公开(公告)日：1997-08-05

申请号：US413960

申请日：1995-03-30

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247 ,  H01L21/265

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US5756385A

公开(公告)日：1998-05-26

申请号：US562198

申请日：1995-11-22

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/981

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物将被离子注入或注入的区域控制在比通过最高分辨率光刻法获得的更小的区域。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US5747359A

公开(公告)日：1998-05-05

申请号：US787852

申请日：1997-01-23

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247 ,  H01L21/465

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物将被离子注入或注入的区域控制在比通过最高分辨率光刻法获得的更小的区域。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US5534456A

公开(公告)日：1996-07-09

申请号：US414333

申请日：1995-03-30

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Henry Chien ,  Gheorghe Samachisa

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L27/11534 ,  H01L27/11543 ,  Y10S438/917 ,  Y10S438/947

摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

摘要翻译： 形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。 在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。 包括分离通道和非分离通道（无选择晶体管）类型的存储单元。 示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。 形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。 通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。 存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

公开(公告)号：US20120199898A1

公开(公告)日：2012-08-09

申请号：US13451009

申请日：2012-04-19

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L27/115

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US20110186799A1

公开(公告)日：2011-08-04

申请号：US13020054

申请日：2011-02-03

申请人： James Kai ,  Henry Chien ,  George Matamis

发明人： James Kai ,  Henry Chien ,  George Matamis

IPC分类号： H01L29/04 ,  H01L21/16 ,  H01L23/52 ,  B82Y99/00

CPC分类号： B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149

摘要： A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

摘要翻译： 非易失性存储单元包括第一电极，操舵元件，与转向元件串联定位的存储元件，多个离散的导电纳米特征，通过绝缘矩阵彼此分离，其中多个离散的纳米 - 特征位于与存储元件直接接触的位置，以及第二电极。 替代的非易失性存储单元包括第一电极，转向元件，与转向元件串联的存储元件，多个分立的绝缘纳米特征，其通过导电矩阵彼此分离，其中多个分立的绝缘 纳米特征位于与存储元件直接接触的位置，以及第二电极。