公开(公告)号：US07579247B2

公开(公告)日：2009-08-25

申请号：US12020296

申请日：2008-01-25

申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC分类号： H01L21/8239

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

公开(公告)号：US07541237B2

公开(公告)日：2009-06-02

申请号：US11867137

申请日：2007-10-04

申请人： Jack H. Yuan ,  Jacob Haskell

发明人： Jack H. Yuan ,  Jacob Haskell

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

摘要： Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

摘要翻译： 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其在衬底顶部的列方向上延伸。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。

公开(公告)号：US07479677B2

公开(公告)日：2009-01-20

申请号：US12020266

申请日：2008-01-25

申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

公开(公告)号：US07416956B2

公开(公告)日：2008-08-26

申请号：US11251386

申请日：2005-10-14

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L21/8228

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76232 ,  H01L27/115

摘要： Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device. This can ensure alignment of the gate and channel regions of a device between trench isolation regions.

摘要翻译： 自对准沟槽填充用于隔离高密度集成电路中的器件。 在器件之间的衬底中形成深而窄的沟槽隔离区域。 沟槽区域包括两个沟槽部分。 位于第二沟槽部分上方的第一沟槽部分填充有沉积的电介质。 第二沟槽部分填充有生长的电介质。 通过生长电介质材料填充下沟槽部分提供在下部分内的电介质材料的均匀分布。 通过沉积介电材料来填充上沟槽部分提供了在上部分中材料的均匀分布，同时还防止例如电介质侵入器件沟道区域。 可以通过蚀刻衬底来形成器件，以在蚀刻形成在器件的衬底上方的一个或多个层之后或部分地形成沟槽区域。 这可以确保器件在沟槽隔离区域之间的栅极和沟道区域的对准。

公开(公告)号：US20080160680A1

公开(公告)日：2008-07-03

申请号：US11617593

申请日：2006-12-28

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L21/82 ,  H01L21/8239

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11568

摘要： Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.

摘要翻译： 提供了用于在非易失性半导体存储器件中的电荷存储区域之间减少耦合的屏蔽板以及用于形成它们的相关技术。 与存储在存储器件的浮动栅极或其他电荷存储区域中的电荷相关联的电场可以耦合到相邻的电荷存储区域，因为这些区域的接近和接近。 屏蔽板可以形成在靠近相邻浮动栅极的相对位线侧的浮动栅极的位线侧。 可以在每个屏蔽板和其相应的相邻电荷存储区域之间形成绝缘层。 绝缘层可以延伸到形成在电荷存储区域上方的控制栅极的上表面的电平。 在这种构造中，可以实施侧壁制造技术以形成绝缘构件和屏蔽板。 每个屏蔽板可以沉积和蚀刻而不需要复杂的掩蔽来连接控制门和屏蔽板。 在一个实施例中，屏蔽板处于浮动电位。

公开(公告)号：US20080157169A1

公开(公告)日：2008-07-03

申请号：US11617598

申请日：2006-12-28

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521

摘要： Shield plates for reduced coupling between charge storage regions in nonvolatile semiconductor memory devices, and associated techniques for forming the same, are provided. Electrical fields associated with charge stored in the floating gates or other charge storage regions of a memory device can couple to neighboring charge storage regions because of the close, and continually decreasing proximity of these regions. A shield plate can be formed adjacent to the bit line sides of floating gates that face opposing bit line sides of adjacent floating gates. Insulating layers can be formed between each shield plate and its corresponding adjacent charge storage region. The insulating layers can extend to the levels of the upper surfaces of the control gates formed above the charge storage regions. In such a configuration, sidewall fabrication techniques can be implemented to form the insulating members and shield plates. Each shield plate can be deposited and etched without complex masking to connect the control gates and shield plates. In one embodiment, the shield plates are at a floating potential.

摘要翻译： 提供了用于在非易失性半导体存储器件中的电荷存储区域之间减少耦合的屏蔽板以及用于形成它们的相关技术。 与存储在存储器件的浮动栅极或其他电荷存储区域中的电荷相关联的电场可以耦合到相邻的电荷存储区域，因为这些区域的接近和接近。 屏蔽板可以形成在靠近相邻浮动栅极的相对位线侧的浮动栅极的位线侧。 可以在每个屏蔽板和其相应的相邻电荷存储区域之间形成绝缘层。 绝缘层可以延伸到形成在电荷存储区域上方的控制栅极的上表面的电平。 在这种构造中，可以实施侧壁制造技术以形成绝缘构件和屏蔽板。 每个屏蔽板可以沉积和蚀刻而不需要复杂的掩蔽来连接控制门和屏蔽板。 在一个实施例中，屏蔽板处于浮动电位。

公开(公告)号：US07211866B2

公开(公告)日：2007-05-01

申请号：US11111129

申请日：2005-04-20

申请人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

发明人： Jack H. Yuan ,  Eliyahou Harari ,  Yupin K. Fong ,  George Samachisa

IPC分类号： H01L27/01

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/7887

摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.

摘要翻译： 通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路 个别浮动门。 衬底中的电荷源和漏极扩散在整个行上连续伸长。 沉积在浮动栅极行之间的场电介质在行之间提供电隔离。 可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。 在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。 包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。 其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

公开(公告)号：US07170131B2

公开(公告)日：2007-01-30

申请号：US11132522

申请日：2005-05-18

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

摘要翻译： 公开了浮动栅极结构，其具有与基底耦合的基极区域和从基底远离基底延伸的窄突起。 在一种形式中，相对大的突起的表面为包围其的控制栅提供增加的表面积，从而增加两者之间的耦合。 在另一种形式中，擦除栅极围绕相对较小的突起卷绕，以便利用突起的尖锐边缘来促进电子从浮动栅极到擦除栅极的隧穿。 在每种情况下，控制或浮动栅极在一个方向上位于浮动栅极的区域内，从而不需要这种存储器单元的附加衬底区域。

公开(公告)号：US06894343B2

公开(公告)日：2005-05-17

申请号：US09860704

申请日：2001-05-18

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also described.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，所述两个沟槽侧壁为相邻电池提供选择晶体管沟道，以及位于沟槽底部的公共源/漏扩散。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 还描述了用于制造这种快闪EEPROM分离通道单元阵列的技术。

公开(公告)号：US06512263B1

公开(公告)日：2003-01-28

申请号：US09667344

申请日：2000-09-22

申请人： Jack H. Yuan ,  Jacob Haskell

发明人： Jack H. Yuan ,  Jacob Haskell

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

摘要： Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.