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102 条记录 (耗时 0.036 秒)

    AUTOMATED DOCUMENT ARCHIVE FOR A DOCUMENT PROCESSING UNIT
    63.
    发明申请
    AUTOMATED DOCUMENT ARCHIVE FOR A DOCUMENT PROCESSING UNIT 审中-公开
    文件处理单元的自动文档存档

    公开(公告)号：US20140222762A1

    公开(公告)日：2014-08-07

    申请号：US13991735

    申请日：2011-12-28

    申请人： Michael F. Fallon ,  Myles Wilde ,  Matthew J. Adiletta ,  Thomas R. Clancy

    发明人： Michael F. Fallon ,  Myles Wilde ,  Matthew J. Adiletta ,  Thomas R. Clancy

    IPC分类号： G06F17/30

    CPC分类号： G06F16/113 ,  H04N1/32101 ,  H04N2201/3205 ,  H04N2201/3222 ,  H04N2201/3278

    摘要： According to some embodiments, a document processing unit may receive information associated with a document to be processed. The document processing unit might comprise, for example, a printer, scanner, copier, facsimile machine, or multi-function device. The document processing unit may then automatically analyze the received information in view of at least one pre-determined archive policy. The document processing unit may then automatically determine, based on the analysis, whether to apply a policy action, associated with the pre-determined archive policy, to the processing of the document. For example, the document processing unit might automatically store a copy of the document in an archive.

    摘要翻译： 根据一些实施例，文档处理单元可以接收与要处理的文档相关联的信息。 文档处理单元可以包括例如打印机，扫描仪，复印机，传真机或多功能设备。 考虑到至少一个预先确定的存档策略，文档处理单元可以自动分析所接收的信息。 然后，文档处理单元可以基于分析自动地确定是否将与预定义的归档策略相关联的策略动作应用于文档的处理。 例如，文档处理单元可能会自动将文档的副本存储在存档中。

    ESTIMATING MOTION OF AN EVENT CAPTURED USING A DIGITAL VIDEO CAMERA
    65.
    发明申请
    ESTIMATING MOTION OF AN EVENT CAPTURED USING A DIGITAL VIDEO CAMERA 有权
    估计使用数字视频摄像机捕获的事件的运动

    公开(公告)号：US20090237503A1

    公开(公告)日：2009-09-24

    申请号：US12053328

    申请日：2008-03-21

    申请人： Matthew J. Adiletta ,  Chengda Yang

    发明人： Matthew J. Adiletta ,  Chengda Yang

    IPC分类号： H04N7/18

    CPC分类号： G06K9/00771 ,  G06K2009/00738 ,  G06T5/50 ,  G06T7/254 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/20076 ,  G06T2207/30232 ,  G08B13/19608 ,  H04N7/188

    摘要： An event aware video system (EAVS) is to capture video frames during a first time period and process events in the video frames before transferring the processed data to a central computing system. The EAVS may establish a present no-event frame from the video frames by marking the last frame as the present no-event frame if the difference between adjacent pair of video frames is less than a threshold value. The EAVS may establish an event frame, wherein a present frame captured after establishing the no-event frame is marked as the event frame if the difference between the present frame and a previous frame is greater than the threshold value. The EAVS may provide event information including motion vectors to a central computing system by performing one-dimensional search on a moving object of the event frame, wherein the motion vectors may represent displacement of objects moving within the moving object.

    摘要翻译： 事件感知视频系统（EAVS）是在第一时间段内捕获视频帧，并且在将处理后的数据传送到中央计算系统之前，在视频帧中处理事件。 如果相邻视频帧对之间的差小于阈值，则EAVS可以通过将最后一帧标记为当前无事件帧来从视频帧建立当前无事件帧。 EAVS可以建立事件帧，其中如果当前帧和先前帧之间的差大于阈值，则在建立无事件帧之后捕获的当前帧被标记为事件帧。 EAVS可以通过对事件帧的移动对象执行一维搜索来向中央计算系统提供包括运动向量的事件信息，其中运动矢量可以表示在运动对象内移动的对象的位移。

    Method and apparatus for performing cyclic redundancy checks
    67.
    发明授权
    Method and apparatus for performing cyclic redundancy checks 有权
    执行循环冗余校验的方法和装置

    公开(公告)号：US07100102B2

    公开(公告)日：2006-08-29

    申请号：US10666693

    申请日：2003-09-18

    申请人： Donald F. Hooper ,  Matthew J. Adiletta ,  Stephanie L. Hirnak

    发明人： Donald F. Hooper ,  Matthew J. Adiletta ,  Stephanie L. Hirnak

    IPC分类号： H03M13/00

    CPC分类号： G11B20/1816

    摘要： Method and apparatus for performing centralized cyclic redundancy checks (CRC). For one embodiment a current thread of execution compares a connection index with that of a previous thread of execution. If they share the same connection index, a CRC calculation may be performed without providing a CRC residue to a centralized CRC unit since the most recently produced CRC residue by would be associated with a preceding sequential cell of the same packet. For an alternative embodiment a current thread of execution requests a CRC calculation and provides a connection index to the centralized CRC unit, which is used to access a content addressable memory (CAM). A hit in the CAM indicates that the CRC unit may use the CRC residue associated with the connection index in the CAM since it would have resulted from a preceding sequential cell.

    摘要翻译： 用于执行集中循环冗余校验（CRC）的方法和装置。 对于一个实施例，当前的执行线程将连接索引与先前的执行线程的索引进行比较。 如果它们共享相同的连接索引，则可以执行CRC计算，而不向集中式CRC单元提供CRC残留，因为最近产生的CRC残留将与相同分组的先前顺序单元相关联。 对于替代实施例，当前的执行线程请求CRC计算，并向用于访问内容可寻址存储器（CAM）的集中式CRC单元提供连接索引。 CAM中的命中指示CRC单元可以使用与CAM中的连接索引相关联的CRC残余，因为它将由先前的顺序单元导致。

    Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits
    68.
    发明授权
    Division method and apparatus including use of a Z--Z plot to select acceptable quotient bits 失效
    分割方法和装置包括使用Z-Z图来选择可接受的商位

    公开(公告)号：US4992968A

    公开(公告)日：1991-02-12

    申请号：US312085

    申请日：1989-02-17

    申请人： Matthew J. Adiletta

    发明人： Matthew J. Adiletta

    IPC分类号： G06F7/537 ,  G06F7/508 ,  G06F7/52 ,  G06F7/535

    CPC分类号： G06F7/535 ,  G06F7/5375

    摘要： An optimized division circuit and a method of implementing the circuit includes the steps of determining a Z--Z plot relationship which represents a relationship between a first divisor ratio proportional to a range of previously determined remainder values divided by the divisor and a second divisor ratio equal to a range of succeeding remainder values divided by the divisor. A completer look-up table is automatically built from the Z--Z plot relationship which includes, for each different valid combination of divisor and next remainder values, either a corresponding quotient digit or a DON'T CARE indicator. A state value, used in the logical implementation of the circuit, is then assigned to each different quotient digit. The circuit includes a divisor multiple formation circuit, a quotient determining circuit and a quotient assimilation circuit. The divisor multiple formation circuit includes a divisor multiple multiplexer. The quotient determining circuit includes a next partial remainder determining circuit and a next quotient digit selection circuit. The quotient assimilation circuit subtracts negative values of quotient digits from positive values to determine a final quotient value.

    摘要翻译： 一种优化的分割电路和一种实现该电路的方法包括以下步骤：确定ZZ绘图关系，该ZZ绘图关系表示与先前确定的余数除以除数的范围成比例的第一因子比与第二除数比之间的关系， 后续余数值的范围除以除数。 从Z-Z绘图关系自动构建一个完整的查找表，对于每个不同的除数和下一个余数值的有效组合，包括相应的商数或DO NOT CARE指示符。 然后将用于电路的逻辑实现的状态值分配给每个不同的商数。 电路包括除数多重形成电路，商确定电路和商同余电路。 除数多重形成电路包括一个除数多路复用器。 商确定电路包括下一部分余数确定电路和下一个商数选择电路。 商同余电路从正值中减去商数的负值，以确定最终商值。