公开(公告)号：US5991545A

公开(公告)日：1999-11-23

申请号：US478730

申请日：1995-06-07

申请人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

发明人： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC分类号： G06F9/28 ,  G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/537 ,  G06F9/30 ,  G06F9/302 ,  G06F9/305 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/22

CPC分类号： G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

摘要： Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

摘要翻译： 这里公开了采用通用寄存器方法的微计算机MCU。 微型计算机能够使用效率低且系统成本低的程序容量小或高程序存储器，同时具有简化指令解码的优点，如具有现有技术的固定长度指令格式的RISC机器，通过 采用固定长度指令格式，其具有功率2但是比馈送到指令执行装置的最大数据字长度的位数更小的位数。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US5954789A

公开(公告)日：1999-09-21

申请号：US648410

申请日：1996-05-15

申请人： Robert K. Yu ,  Nasima Parveen ,  J. Arjun Prabhu

发明人： Robert K. Yu ,  Nasima Parveen ,  J. Arjun Prabhu

IPC分类号： G06F7/537 ,  G06F7/00 ,  G06F7/483 ,  G06F7/506 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F7/4873 ,  G06F7/49952

摘要： Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

摘要翻译： 修改商数字选择逻辑，以防止等于负除数的部分余数发生。 如果结果是精确的，增强的商数选择功能可以防止工作部分余数变为否定，当实际部分余数为零时，选择零的商数为零，而不是1的商数。 使用五位估计的部分余数，其中高四位为零，检测到第四最高有效位的可能进位传播。 这可以通过查看第五最高有效和并且携带冗余部分余数的位来实现。 如果它们均为零，则从该位位置进入估计的部分余数的最低有效位置的进位传播是不可能的，并且选择零的商数。 这提供了一个周期的节省，因为在计算粘性位之前不再需要恢复负部分余数。 额外的硬件被消除，因为不再需要提供任何额外的机制来恢复初步的最终部分剩余。 改进了延迟，因为不需要额外的周期时间来恢复负的初步部分余数。 在替代实施例中，其中估计的部分余数的高四位是1，而第五最高有效位为零，则选择负数的商数。 该替代实施例允许在所有舍入模式中的正确精确结果，包括向正或负无穷大舍入。

公开(公告)号：US5910910A

公开(公告)日：1999-06-08

申请号：US880408

申请日：1997-06-23

申请人： Guy L. Steele, Jr.

发明人： Guy L. Steele, Jr.

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552

CPC分类号： G06F7/5525 ,  G06F7/535

摘要： A circuit and method for accelerating the division algorithm and square root operations relating to integers or floating-point numbers. Minimization of the number of gate delays per quotient digit generated is achieved through the use of triply-redundant representation of the partial remainder and a fully-overlapped quotient digit prediction scheme suitable for logic implementation. Moreover, faster quotient digit selection is achieved by prescaling the dividend and divisor.

摘要翻译： 一种用于加速与整数或浮点数相关的除法算法和平方根操作的电路和方法。 通过使用部分余数的三重冗余表示和适合于逻辑实现的完全重叠的商数预测方案来实现生成的每个商数的门延迟数量的最小化。 此外，通过对股息和除数进行预分解可以实现更快的商数选择。

公开(公告)号：US5870323A

公开(公告)日：1999-02-09

申请号：US928073

申请日：1997-09-11

申请人： J. Arjun Prabhu ,  Grzegorz B. Zyner

发明人： J. Arjun Prabhu ,  Grzegorz B. Zyner

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F17/10

CPC分类号： G06F7/535 ,  G06F7/5525

摘要： In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0, and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

摘要翻译： 在硬件SRT划分和平方根尾数单位中，使用每个周期三个商数的最大商选择重叠。 有效的基数8实现级联三个部分余数计算电路并与三个商选择电路重叠。 两个进位保存加法器通过添加除数而不添加任何东西并分别添加除数的二进制补码来推测计算对应于商数的每个可能值-1,0和+1的可能的结果部分余数， 从而缩短产生单个商数的单个SRT迭代的关键路径。 推测计算可能产生的部分余数的两个进位保存加法器的传播延迟被商选择逻辑的较长延迟掩蔽。

公开(公告)号：US5748518A

公开(公告)日：1998-05-05

申请号：US510712

申请日：1995-08-03

申请人： David Vivian Jaggar

发明人： David Vivian Jaggar

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F9/302

CPC分类号： G06F7/535 ,  G06F2207/5353

摘要： A microprocessor is described having an arithmetic unit 8 that includes a dedicated hardware divider. The hardware divider is responsive to a plurality of different divide instruction codes to generate respective multi-bit portions of a quotient. Each divide instruction can be early terminated when the partial remainder is detected as being zero. Furthermore, subsequent divide instructions to calculate the remaining bits of the quotient can be skipped in response to a flag (Zflag) set within a current programming status register 28. In the described embodiment, a 32-bit divisor and 64-bit dividend serve to produce a 32-bit quotient and a 32-bit remainder. The generation of the 32-bit quotient takes place in response to four different divide instruction codes each responsible for generating a respective 8-bit portion of the quotient.

摘要翻译： 描述了具有包括专用硬件分频器的算术单元8的微处理器。 硬件分频器响应于多个不同的除法指令代码来产生商的相应多位部分。 当部分余数被检测为零时，可以提前终止每个除法指令。 此外，响应于在当前编程状态寄存器28内设置的标志（Zflag）可以跳过用于计算商的剩余位的后续除法指令。在所描述的实施例中，32位除数和64位除数用于 产生32位商和32位余数。 响应于四个不同的除法指令代码，发生32位商的产生，每个除法指令代码负责生成商的相应的8位部分。

公开(公告)号：US5272660A

公开(公告)日：1993-12-21

申请号：US891095

申请日：1992-06-01

申请人： Paul C. Rossbach

发明人： Paul C. Rossbach

IPC分类号： G06F7/537 ,  G06F7/483 ,  G06F7/52 ,  G06F7/535 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5375 ,  G06F7/4873

摘要： A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.

摘要翻译： 一种用于在数据处理器中使用单个修改的SRT分频器执行整数和浮点除法运算的方法和装置。 使用归一化正尾数（股利和除数）的SRT除法执行浮点和整数除法。 整数分割共享浮点电路的部分，然而，在执行整数除法运算期间，操作序列被修改。 SRT分频器在迭代循环之前和之后执行一系列操作，以将整数除数和股息重新配置为SRT算法对浮点尾数所需的数据路径表示。 在迭代循环期间，商位被选择并用于产生中间部分余数。 商位也被输入到累积最终商尾数的商寄存器。 使用全尾数加法器来产生最后的余数。

公开(公告)号：US5107453A

公开(公告)日：1992-04-21

申请号：US379114

申请日：1989-07-13

申请人： Masahiro Nomura

发明人： Masahiro Nomura

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F9/302

CPC分类号： G06F7/535 ,  G06F9/3001 ,  G06F2207/5353

摘要： A data processor using a temporary register for temporarily storing a dividend data and a divisor data, sign flags for indicating respective signs of the dividend and the divisor, and an arithmetic and logic unit (ALU) coupled to the temporary register and having an arithmetic logic operation function required for execution of a division operation and a two's compliment obtaining operation. A microsequencer is provided to control the ALU so as to cause the ALU to execute a given instruction. The microsequencer generates a two's complement obtaining operation instruction signal, and an operation control circuit is coupled to the sign flags and is connected to receive the two's complement obtaining operation instruction signal. The operation control circuit operates to control the ALU in accordance with an output of the sign flags so as to cause the ALU to execute a two's complement obtaining operation, or to substantially invalidate the two's complement obtaining operation of the ALU regardless of the two's complement obtaining operation instruction signal.

公开(公告)号：US5031136A

公开(公告)日：1991-07-09

申请号：US239243

申请日：1990-05-07

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu

IPC分类号： G06F7/48 ,  G06F7/52 ,  G06F7/537 ,  G06F7/544

CPC分类号： G06F7/544 ,  G06F7/4824 ,  G06F7/523 ,  G06F7/5338 ,  G06F7/5375

摘要： A high speed arithmetic processor includes an array of arithmetic cells which operate on digits internally represented in a signed-digit binary format. Certain of these cells perform subtraction operations on two ordinary binary digits, and produce the difference in a 2-bit signed-digit binary format, without requiring a separate ordinary binary to signed-digit binary converter.

摘要翻译： 一个高速运算处理器包括一个运算数组的运算单元，这些运算单元以一个有符号位二进制格式内部表示的数字运算。 这些小区中的某些小区对两个普通二进制数字执行减法运算，并产生2位有符号数位二进制格式的差异，而不需要单独的普通二进制到有符号位二进制转换器。

公开(公告)号：US4975868A

公开(公告)日：1990-12-04

申请号：US339279

申请日：1989-04-17

申请人： Donald L. Freerksen

发明人： Donald L. Freerksen

IPC分类号： G06F7/487 ,  G06F7/506 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537

CPC分类号： G06F7/4876 ,  G06F7/535 ,  G06F7/5375 ,  G06F7/4873 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49947

摘要： A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic removes the bias from one operand exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.

公开(公告)号：US4868777A

公开(公告)日：1989-09-19

申请号：US95525

申请日：1987-09-10

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu ,  Naofumi Takagi

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu ,  Naofumi Takagi

IPC分类号： G06F7/48 ,  G06F7/52 ,  G06F7/537 ,  G06F7/544

CPC分类号： G06F7/544 ,  G06F7/4824 ,  G06F7/523 ,  G06F7/5375

摘要： An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.

摘要翻译： 描述了以高速执行连续相乘操作的运算处理器电缆，其中内部表示为进位保存或有符号数字表达式的结果乘积可以以该形式直接输入作为下一个连续乘法运算的乘数。 此外，提供了一个乘法器重新编码器电路，其以进位保存或有符号位表达式的形式将二进制乘法器重新编码为基数4的有符号数字，以进一步提高操作速度。