公开(公告)号：US20090280627A1

公开(公告)日：2009-11-12

申请号：US12119384

申请日：2008-05-12

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael Hargrove

IPC: H01L21/322

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract translation: 提供一种制造半导体晶体管器件的方法。 制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。 然后，围绕栅极结构的侧壁形成间隔物。 接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。 在该步骤中，栅极结构和间隔物用作离子注入掩模。 离子在半导体材料中形成非晶化区域。 此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。 此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

公开(公告)号：US20090228132A1

公开(公告)日：2009-09-10

申请号：US12045081

申请日：2008-03-10

Applicant: Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

Inventor： Kevin R. Lensing ,  Alok Vaid ,  Rohit Pal

IPC: G06F17/00

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method includes receiving a performance distribution for a plurality of devices to be fabricated in a semiconductor process flow. A performance target for a particular device is specified based on the performance distribution. A stressed material is formed in a recess adjacent a gate electrode of a transistor in the particular device in accordance with at least one operating recipe. The recess is spaced from the gate electrode by a gate proximity distance. A target value for the gate proximity distance is determined based on the performance target. At least one parameter of the operating recipe is determined based on the target value for the gate proximity distance.

Abstract translation: 一种方法包括接收要在半导体工艺流程中制造的多个器件的性能分布。 基于性能分布指定特定设备的性能目标。 根据至少一个操作配方，在与特定装置中的晶体管的栅电极相邻的凹部中形成应力材料。 凹槽与栅电极隔开一个栅极接近距离。 基于性能目标确定门接近距离的目标值。 基于门接近距离的目标值确定操作配方的至少一个参数。

公开(公告)号：US20080237811A1

公开(公告)日：2008-10-02

申请号：US11694057

申请日：2007-03-30

Applicant: Rohit Pal ,  David F. Brown

Inventor： Rohit Pal ,  David F. Brown

IPC: H01L23/544

CPC classification number: H01L22/20

Abstract: A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.

Abstract translation: 用于捕获工艺历史的方法包括至少执行用于在半导体衬底上形成特征的第一工艺。 在执行第一处理之后，在半导体基板的第一区域上形成第一盖。 执行至少第二过程，用于在除了第一区域之外的第二区域中形成特征，同时将第一盖留在适当位置，从而防止第一盖子覆盖的第一区域中的特征暴露于第二过程。 在第一区域中测量第一特征的第一特征，并且测量第二区域中的第二特征的第二特征。 晶片包括设置在第一区域中的第一部分完成特征。 在第一部分完成的特征之上形成第一盖。 第二部分完成的特征被布置在不同于第一区域的晶片的第二区域中。 第二部分完成的功能处于完成的后期，而不是第一部分完成的功能。