公开(公告)号：US07475194B2

公开(公告)日：2009-01-06

申请号：US11968481

申请日：2008-01-02

申请人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

发明人： Jos Accapadi ,  Andrew Dunshea ,  Greg R. Mewhinney ,  Mysore Sathyanaranyana Srinivas

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0891

摘要： A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

摘要翻译： 计算机实现的方法，装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联，其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较，以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目，则标记高速缓存条目，其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。

公开(公告)号：US07454570B2

公开(公告)日：2008-11-18

申请号：US11006371

申请日：2004-12-07

申请人： Andrew Dunshea ,  Satya Prakash Sharma ,  Mysore Sathyanarayana Srinivas

发明人： Andrew Dunshea ,  Satya Prakash Sharma ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F12/00

CPC分类号： G06F12/0837 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857

摘要： A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation. The sync causes all values updated by the intermediate store operations to be flushed out to the point of coherency and be visible to all processors.

摘要翻译： 具有弱有序体系结构的多处理器数据处理系统（MDPS）提供处理逻辑，用于在运行良好的应用的每个存储指令之后基本上消除发出同步指令。 良好的应用程序的指令由弱有序的处理器转换和执行。 处理逻辑包括一个锁定地址跟踪实用程序（LATU），它提供一种算法和一个锁定地址表，当弱锁定处理器获取锁时，锁存地址被存储在该地址中。 当在指令流中遇到存储指令时，LATU将存储指令的目标地址与锁定地址表进行比较。 如果目标地址与其中一个锁定地址匹配，指示存储指令是相应的解锁指令（或锁定释放指令），则在存储操作之前发出同步指令。 同步使得由中间存储操作更新的所有值被刷新到一致性点，并且对于所有处理器可见。

公开(公告)号：US07318142B2

公开(公告)日：2008-01-08

申请号：US11463100

申请日：2006-08-08

申请人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Li Li ,  Grover Herbert Neuman ,  Mysore Sathyanarayana Srinivas ,  David Alan Hepkin

发明人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Li Li ,  Grover Herbert Neuman ,  Mysore Sathyanarayana Srinivas ,  David Alan Hepkin

IPC分类号： G06F12/06

CPC分类号： G06F12/023

摘要： A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).

摘要翻译： 提供了一种基于当前系统内存条件动态更改虚拟内存管理器（VMM）顺序访问预读设置的系统和方法。 使用用户设置的顺序访问读取前值可以执行正常的VMM操作。 当检测到低内存时，系统会根据自由空间量是否很低或已经达到极低的水平，关闭顺序访问预读操作或者减小最大页面前提（maxpgahead）值。 改变的VMM顺序访问预读状态在有足够的可用空间可用之前保持有效，以便可以执行正常的VMM顺序访问预读操作（此时，改变的顺序访问读取前置值被重置为其原始级别） 。

公开(公告)号：US09201703B2

公开(公告)日：2015-12-01

申请号：US11422656

申请日：2006-06-07

申请人： Andrew Dunshea ,  Diane G. Flemming

发明人： Andrew Dunshea ,  Diane G. Flemming

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/50

CPC分类号： G06F9/5077

摘要： Sharing kernel services among kernels, including receiving, by a partition manager from an application in a logical partition, a first system call for a kernel service from a first kernel, the first system call having form and content compatible with the first kernel, generating, in dependence upon the first system call, a second system call for the kernel service from a second kernel, the second system call having form and content compatible with the second kernel, and sending the second system call through the partition manager to the second kernel for execution.

摘要翻译： 在内核之间共享内核服务，包括由分区管理器从逻辑分区中的应用程序接收来自第一内核的内核服务的第一系统调用，第一系统调用具有与第一内核兼容的形式和内容， 根据第一系统调用，第二系统调用来自第二内核的内核服务，第二系统调用具有与第二内核兼容的形式和内容，并且通过分区管理器将第二系统调用发送到第二内核，用于 执行。

公开(公告)号：US08447955B2

公开(公告)日：2013-05-21

申请号：US12259699

申请日：2008-10-28

申请人： Andrew Dunshea ,  Satya Prakash Sharma ,  Mysore Sathyanarayana Srinivas

发明人： Andrew Dunshea ,  Satya Prakash Sharma ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/30

CPC分类号： G06F12/0837 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857

摘要： A multiprocessor data processing system (MDPS) with a weakly-ordered architecture providing processing logic for substantially eliminating issuing sync instructions after every store instruction of a well-behaved application. Instructions of a well-behaved application are translated and executed by a weakly-ordered processor. The processing logic includes a lock address tracking utility (LATU), which provides an algorithm and a table of lock addresses, within which each lock address is stored when the lock is acquired by the weakly-ordered processor. When a store instruction is encountered in the instruction stream, the LATU compares the target address of the store instruction against the table of lock addresses. If the target address matches one of the lock addresses, indicating that the store instruction is the corresponding unlock instruction (or lock release instruction), a sync instruction is issued ahead of the store operation. The sync causes all values updated by the intermediate store operations to be flushed out to the point of coherency and be visible to all processors.

摘要翻译： 具有弱有序体系结构的多处理器数据处理系统（MDPS）提供处理逻辑，用于在运行良好的应用的每个存储指令之后基本上消除发出同步指令。 良好的应用程序的指令由弱有序的处理器转换和执行。 处理逻辑包括一个锁定地址跟踪实用程序（LATU），它提供一种算法和一个锁定地址表，当弱锁定处理器获取锁时，锁存地址被存储在该地址中。 当在指令流中遇到存储指令时，LATU将存储指令的目标地址与锁定地址表进行比较。 如果目标地址与其中一个锁定地址匹配，指示存储指令是相应的解锁指令（或锁定释放指令），则在存储操作之前发出同步指令。 同步使得由中间存储操作更新的所有值被刷新到一致性点，并且对于所有处理器可见。

公开(公告)号：US07721047B2

公开(公告)日：2010-05-18

申请号：US11006112

申请日：2004-12-07

申请人： Andrew Dunshea ,  Diane Garza Flemming

发明人： Andrew Dunshea ,  Diane Garza Flemming

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0864 ,  G06F12/1045

摘要： In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the kernel. The application designs an optimum cache footprint for a data set from said application. The objects, advantages and features of the present invention will become apparent from the following detailed description. In one embodiment of the present invention, the application transmits a memory reallocation order to a memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to the memory manager further comprises the application transmitting a memory reallocation order containing the optimum cache footprint to the memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to a memory manager further comprises the application transmitting the memory reallocation order containing to a reallocation services tool within the memory manager.

摘要翻译： 鉴于上述情况，现有技术的高速缓存优化技术的缺点在于本发明提供了可以优化高速缓存利用的改进的方法，系统和计算机程序产品。 在一个实施例中，应用程序从内核服务请求内核缓存映射，并且应用程序接收内核。 该应用程序为来自所述应用的数据集设计了最佳缓存占用。 从下面的详细描述中，本发明的目的，优点和特征将变得显而易见。 在本发明的一个实施例中，应用程序将存储器重新分配顺序发送到存储器管理器。 在本发明的一个实施例中，向存储器管理器发送存储器重分配顺序的应用程序的步骤还包括向存储器管理器发送包含最佳高速缓存占用空间的存储器重新分配顺序的应用程序。 在本发明的一个实施例中，向存储器管理器发送存储器重新分配顺序的应用程序的步骤还包括将包含在存储器管理器内的重新分配服务工具的​​存储器重新分配顺序传送的应用。

公开(公告)号：US20090254730A1

公开(公告)日：2009-10-08

申请号：US12478830

申请日：2009-06-05

申请人： Andrew Dunshea ,  Jos Manuel Accapadi ,  Catherine Moriarty Nunez

发明人： Andrew Dunshea ,  Jos Manuel Accapadi ,  Catherine Moriarty Nunez

IPC分类号： G06F12/02

CPC分类号： G06F12/1009 ,  Y10S707/99953 ,  Y10S707/99957

摘要： A method, system, and program for managing memory page requests in a multi-processor data processing system determines a threshold value of available memory, and dynamically adjusts an allocation time to fulfill a page request if the available memory is below a threshold value. The allocation time to fulfill the page request is based upon a percentage of available memory pages once a page stealer commences a scan for pages. An allocation wait time is inversely proportionally adjusted depending upon the percentage of available memory. The allocation wait time has a duration that increases in time as the percentage of available memory decreases and decreases in time as the percentage of available memory increases. More specifically, an average time per page to allocate a page including a scan time for the scan in computing the average time is determined. Then a tunable value is applied to the average time to determine a wait time. In a preferred embodiment, user defined values are received that would control the allocation wait time before fulfilling a page request.

摘要翻译： 用于管理多处理器数据处理系统中的存储器页面请求的方法，系统和程序确定可用存储器的阈值，并且如果可用存储器低于阈值，则动态地调整分配时间以满足页面请求。 一旦页面窃取器开始扫描页面，则完成页面请求的分配时间基于可用内存页面的百分比。 分配等待时间根据可用内存的百分比进行反比例调整。 分配等待时间具有随时间增加的持续时间，随着可用内存的百分比的增加，可用内存的百分比随时间而减少。 更具体地，确定在计算平均时间时分配包括用于扫描的扫描时间的页面的每页的平均时间。 然后将可调值应用于平均时间以确定等待时间。 在优选实施例中，接收用户定义的值，其将在满足页面请求之前控制分配等待时间。

公开(公告)号：US20090113239A1

公开(公告)日：2009-04-30

申请号：US11924192

申请日：2007-10-25

申请人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Miho Ogishima ,  Suzanne Shi

发明人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Miho Ogishima ,  Suzanne Shi

IPC分类号： G06F9/30 ,  G06F11/07 ,  G06F9/312

CPC分类号： G06F9/30101

摘要： A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register.

摘要翻译： 一种用于使用指令跟踪寄存器的计算机实现的方法，装置和计算机可用程序产品。 在一个实施例中，响应于执行与程序代码相关联的指令，更新多个处理器寄存器中的目标处理器寄存器中的值。 响应更新目标处理器寄存器中的值，将指令的地址从指令地址寄存器复制到与目标处理器寄存器相关联的指令跟踪寄存器中。 指令跟踪寄存器保存更新存储在目标处理器寄存器中的值的指令的地址。

公开(公告)号：US20070288941A1

公开(公告)日：2007-12-13

申请号：US11422656

申请日：2006-06-07

申请人： Andrew Dunshea ,  Diane G. Flemming

发明人： Andrew Dunshea ,  Diane G. Flemming

IPC分类号： G06F9/46

CPC分类号： G06F9/5077

摘要： Sharing kernel services among kernels, including receiving, by a partition manager from an application in a logical partition, a first system call for a kernel service from a first kernel, the first system call having form and content compatible with the first kernel, generating, in dependence upon the first system call, a second system call for the kernel service from a second kernel, the second system call having form and content compatible with the second kernel, and sending the second system call through the partition manager to the second kernel for execution.

摘要翻译： 在内核之间共享内核服务，包括由分区管理器从逻辑分区中的应用程序接收来自第一内核的内核服务的第一系统调用，第一系统调用具有与第一内核兼容的形式和内容， 根据第一系统调用，第二系统调用来自第二内核的内核服务，第二系统调用具有与第二内核兼容的形式和内容，并且通过分区管理器将第二系统调用发送到第二内核，用于 执行。

公开(公告)号：US20070136721A1

公开(公告)日：2007-06-14

申请号：US11301113

申请日：2005-12-12

申请人： Andrew Dunshea ,  Diane Flemming

发明人： Andrew Dunshea ,  Diane Flemming

IPC分类号： G06F9/445

CPC分类号： G06F9/5077 ,  G06F8/60

摘要： Sharing a kernel of an operating system among logical partitions, including installing in a partition manager a kernel of a type used by a plurality of logical partitions; installing in the partition manager generic data structures specifying computer resources assigned to each of the plurality of logical partitions; and providing, by the kernel to the logical partitions, kernel services in dependence upon the generic data structures.

摘要翻译： 在逻辑分区之间共享操作系统的内核，包括在分区管理器中安装由多个逻辑分区使用的类型的内核; 在所述分区管理器中安装指定分配给所述多个逻辑分区中的每一个的计算机资源的通用数据结构; 并且由内核向逻辑分区提供依赖于通用数据结构的内核服务。