公开(公告)号：US08832416B2

公开(公告)日：2014-09-09

申请号：US11753005

申请日：2007-05-24

申请人： Wen-Tzer Thomas Chen ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mysore Sathyanarayana Srinivas

发明人： Wen-Tzer Thomas Chen ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F11/34

CPC分类号： G06F11/3409 ,  G06F11/3471 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.

摘要翻译： 信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。 信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。 在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。 在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。 操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

公开(公告)号：US20120042131A1

公开(公告)日：2012-02-16

申请号：US12856682

申请日：2010-08-15

申请人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

发明人： Diane Garza Flemming ,  William A. Maron ,  Ram Raghavan ,  Mysore Sathyanarayana Srinivas ,  Basu Vaidyanathan

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0284 ,  G06F2212/502 ,  G06F2212/604

摘要： An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

摘要翻译： 提供了一种方法来识别对应于在计算机系统上运行的不同分区的高速缓存扩展大小。 该方法利用来自系统存储器区域的第一存储器分配来扩展与包括在处理器的硅衬底中的第一处理核心相关联的第一硬件高速缓存，系统存储器区域在硅衬底外部，并且第一存储器分配对应于 多个缓存扩展大小中的一个对应于在计算机系统上运行的分区之一。 该方法进一步扩展与第二处理核心相关联的第二硬件高速缓存，该第二处理核心还包括在处理器的硅衬底中，具有来自系统存储区域的第二存储器分配，其中第二存储器分配对应于对应于不同分区的另一个高速缓存扩展大小 正在由第二处理核心执行。

公开(公告)号：US07962913B2

公开(公告)日：2011-06-14

申请号：US12342352

申请日：2008-12-23

申请人： Jos Manuel Accapadi ,  Mathew Accapadi ,  Andrew Dunshea ,  Mark Elliott Hack ,  Agustin Mena, III ,  Mysore Sathyanarayana Srinivas

发明人： Jos Manuel Accapadi ,  Mathew Accapadi ,  Andrew Dunshea ,  Mark Elliott Hack ,  Agustin Mena, III ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46 ,  G06F13/24

CPC分类号： G06F9/5027 ,  G06F9/4812

摘要： Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

摘要翻译： 提供方法，系统和计算机程序产品用于在多处理器计算机中调度线程。 实施例包括选择要发送到处理器的准备队列中的线程，并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。 如果在与线程相关联的线程控制块中设置中断屏蔽标志，则实施例通常包括选择处理器，将所选择的处理器的当前处理器优先级寄存器设置为最不利，并将线程从就绪队列调度到所选择的处理器 。 在一些实施例中，将所选择的处理器的当前处理器优先级寄存器设置为最不利的是通过在当前处理器优先级寄存器中存储与最高中断优先级相关联的值来执行。

公开(公告)号：US07962677B2

公开(公告)日：2011-06-14

申请号：US12173211

申请日：2008-07-15

申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

IPC分类号： G06F13/00

CPC分类号： G06F9/485 ,  G06F9/4881

摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

公开(公告)号：US07698707B2

公开(公告)日：2010-04-13

申请号：US12036804

申请日：2008-02-25

申请人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

发明人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/30 ,  G06F9/46

CPC分类号： G06F9/4881 ,  G06F2209/483

摘要： Identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.

摘要翻译： 通过计算在SMT处理器上运行两个线程时发生的性能指标（例如每个指令周期（CPI））来提供在同时多线程（SMT）处理器环境中识别兼容线程。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值，则记录指示兼容性的信息。 当线程即将完成时，调度程序将查看完成线程所属的运行队列，以调度另一个线程。 调度程序标识（1）与SMT处理器上仍然运行的线程（即，即将完成的线程）兼容的线程，以及（2）准备执行。 持续更新CPI数据，以便不断地识别彼此兼容的线程。

公开(公告)号：US20100017551A1

公开(公告)日：2010-01-21

申请号：US12173211

申请日：2008-07-15

申请人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

发明人： William A. Maron ,  Diane Garza Flemming ,  Ghadir Robert Gholami ,  Mysore Sathyanarayana Srinivas ,  Octavian Florin Herescu

IPC分类号： G06F13/14

CPC分类号： G06F9/485 ,  G06F9/4881

摘要： A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.

摘要翻译： 提供了一种方法，编程介质和系统，其中系统总线流量由实时数据调节。 操作系统（OS）能够从固件（FW）获取信息，以确定是否已达到资源阈值。 这通过在总线请求重试速率达到预定数量时产生中断来标记OS来实现。 系统固件在此机制中起着不可或缺的作用，应该被解释为一个通用术语，也可以包括管理程序技术。 系统固件将通过例如固件产生的中断来向总线请求重试率报告给操作系统。 操作系统可能与内核守护程序/服务类似，以拦截中断通知。 在最简单的情况下，守护程序/服务将根据固件的反馈来确定阈值是否得到满足。 如果是这样，它将生成一个系统调用，以便通过操作系统可调整来调节流量。 在一个示例中，使用系统调用将减少每个内核的同时多线程（SMT）线程数。 这有效地节省了每个内核的逻辑线程数量，并有效地缓解了总线请求饱和度。

公开(公告)号：US20090183169A1

公开(公告)日：2009-07-16

申请号：US11972361

申请日：2008-01-10

申请人： Men-Chow Chiang ,  Sujatha Kashyap ,  Mysore Sathyanarayana Srinivas

发明人： Men-Chow Chiang ,  Sujatha Kashyap ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46 ,  G06F12/08

CPC分类号： G06F12/1036 ,  G06F9/5061

摘要： A system and method for allowing jobs originating from different partitions to simultaneously utilize different hardware threads on a processor by concatenating partition identifiers with virtual page identifiers within a processor's translation lookaside buffer is presented. The device includes a translation lookaside buffer that translates concatenated virtual addresses to system-wide real addresses. The device generates concatenated virtual addresses using a partition identifier, which corresponds to a job's originating partition, and a virtual page identifier, which corresponds to the executing instruction, such as an instruction address or data address. In turn, each concatenated virtual address is different, which translates in the translation lookaside buffer to a unique system-wide real address. As such, jobs originating from different partitions are able to simultaneously execute on the device and, therefore, fully utilize each of the device's hardware threads.

摘要翻译： 提出了一种用于允许源自不同分区的作业同时利用处理器中的不同硬件线程的系统和方法，其通过将分区标识符与处理器的翻译后备缓冲器内的虚拟页面标识符相连接。 该设备包括翻译后备缓冲区，将连接的虚拟地址转换为系统范围的实际地址。 设备使用对应于作业的始发分区的分区标识符和对应于执行指令（诸如指令地址或数据地址）的虚拟页面标识符来生成级联的虚拟地址。 反过来，每个连接的虚拟地址是不同的，这将翻译后备缓冲区转换为唯一的系统范围的实际地址。 因此，源自不同分区的作业能够在设备上同时执行，并因此充分利用设备的每个硬件线程。

公开(公告)号：US20090106762A1

公开(公告)日：2009-04-23

申请号：US12342352

申请日：2008-12-23

申请人： Jos Manuel Accapadi ,  Matthew Accapadi ,  Andrew Dunshea ,  Mark Elliot Hack ,  Augustin Mena, III ,  Mysore Sathyanarayana Srinivas

发明人： Jos Manuel Accapadi ,  Matthew Accapadi ,  Andrew Dunshea ,  Mark Elliot Hack ,  Augustin Mena, III ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46

CPC分类号： G06F9/5027 ,  G06F9/4812

摘要： Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.

摘要翻译： 提供方法，系统和计算机程序产品用于在多处理器计算机中调度线程。 实施例包括选择要发送到处理器的准备队列中的线程，并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。 如果在与线程相关联的线程控制块中设置中断屏蔽标志，则实施例通常包括选择处理器，将所选择的处理器的当前处理器优先级寄存器设置为最不利，并将线程从就绪队列调度到所选择的处理器 。 在一些实施例中，将所选择的处理器的当前处理器优先级寄存器设置为最不利的是通过在当前处理器优先级寄存器中存储与最高中断优先级相关联的值来执行。

公开(公告)号：US07353517B2

公开(公告)日：2008-04-01

申请号：US10671057

申请日：2003-09-25

申请人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

发明人： Jos Manuel Accapadi ,  Andrew Dunshea ,  Dirk Michel ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/46

CPC分类号： G06F9/5083

摘要： A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.

摘要翻译： 提供了一种利用多个SMT处理器的同时多线程（SMT）处理器环境中调度线程的系统和方法。 识别在每个SMT处理器上运行的执行不良线程。 被识别后，执行不良的线程被移动到不同的SMT处理器。 捕获关于线程性能的数据。 在一个实施例中，该数据包括每个线程的CPI值。 当线程移动时，与线程及其在移动时的性能相关的数据与时间戳一起被记录。 关于先前移动的数据用于确定线程的性能是否随着移动而改善。

公开(公告)号：US20060206891A1

公开(公告)日：2006-09-14

申请号：US11077324

申请日：2005-03-10

申请人： William Joseph Armstrong ,  Timothy Richard Marchini ,  Naresh Nayar ,  Bret Ronald Olszewski ,  Mysore Sathyanarayana Srinivas

发明人： William Joseph Armstrong ,  Timothy Richard Marchini ,  Naresh Nayar ,  Bret Ronald Olszewski ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F9/455

CPC分类号： G06F9/45537

摘要： A system, computer program product and method of logically partitioning a multiprocessor system are provided. The system is first partitioned into a plurality of partitions and each partition is assigned a percentage of the resources of the system. However, to provide the system with virtual machine capability, virtual resources, rather than physical resources, are assigned to the partitions. The virtual resources are mapped and bound to the physical resources that are available in the system. Because of the virtual machine capability of the system, logical partitions that are in need of resources that are assigned to other partitions are allowed to use those resources if the resources are idle.

摘要翻译： 提供了一种逻辑划分多处理器系统的系统，计算机程序产品和方法。 该系统首先被划分成多个分区，并且每个分区被分配一部分系统的资源。 然而，为了向系统提供虚拟机能力，将虚拟资源而不是物理资源分配给分区。 虚拟资源被映射并绑定到系统中可用的物理资源。 由于系统的虚拟机能力，如果资源空闲，则允许需要分配给其他分区的资源的逻辑分区使用这些资源。