公开(公告)号：US20090077361A1

公开(公告)日：2009-03-19

申请号：US11694344

申请日：2007-03-30

申请人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

发明人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

IPC分类号： G06F9/30

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop

摘要翻译： 公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。 在一个实施例中，装置包括检测逻辑和虚拟逻辑。 检测逻辑是检测访客是否正在执行自旋循环。 虚拟化逻辑是根据检测逻辑检测客人正在执行自旋循环的方式将设备的控制从客户机传送到主机

公开(公告)号：US07191349B2

公开(公告)日：2007-03-13

申请号：US10330622

申请日：2002-12-26

申请人： Shivnandan D. Kaushik ,  John W. Horigan ,  Alon Naveh ,  James B. Crossland

发明人： Shivnandan D. Kaushik ,  John W. Horigan ,  Alon Naveh ,  James B. Crossland

IPC分类号： G06F1/00 ,  G06F1/30 ,  G06F1/32

CPC分类号： G06F9/3851 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/4812 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D10/24

摘要： A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

摘要翻译： 一种用于处理器功率状态识别分配最低优先级中断的机制的方法。 一个实施例的方法包括从第一组件接收第一功率状态信息和从第二组件接收第二功率状态信息。 还接收来自第一分量的第一任务优先级信息和来自第二分量的第二任务优先级。 接收来自第一设备的用于维修的中断请求。 评估第一和第二组件的功率状态和任务优先级信息，以确定哪个组件应该服务于中断请求。 选择第一组件或第二组件作为目的组件，以基于功率状态和任务优先级信息来服务中断请求。 中断请求被传送到目标组件。