摘要:
In a UWB antenna having an upper dielectric member, a lower dielectric member, and a conductor pattern interposed therebetween, the conductor pattern has a feeding point at a generally center portion of a front surface of the antenna. The conductor pattern further has an inverted triangular portion including a right tapered portion and a left tapered portion extending from the feeding point towards right and left side surfaces of the antenna, respectively. A main expanding portion expands from an upper side of the inverted triangular portion. A right expanding portion and a left expanding portion expand from the right and the left tapered portions of the inverted triangular portion, respectively.
摘要:
A UWB antenna has an upper dielectric, a lower dielectric, and a conductive pattern sandwiched therebetween. The conductive pattern has a vertex apart from a feeding point with a predetermined gap. The conductive pattern has a reversed triangular portion having a right-hand taper part and a left-side taper part which widen from the feeding point at a predetermined angle toward a right-hand side surface and a left-hand side surface, respectively, and a semicircular portion having a base side being in contact with an upper side of the reversed triangular portion. The UWB antenna further has a feeding pattern connected to the feeding point, whereby carrying out feed from the feeding pattern to the conductive pattern by electromagnetic coupling.
摘要:
An electromagnetic coupling type four-point feeding loop antenna (10) comprises a cylindrical body (11) formed by rounding a flexible insulator film member (20) around a central axis (O) in a cylindrical fashion and a loop portion (12) made of conductor that is formed on the cylindrical body along a peripheral surface thereof around the central axis in a loop fashion. In order to feed to the loop portion at four points, four feeders (13) are formed on the peripheral surface of the cylindrical body. Between the loop portion and each of the four feeders, a gap (&dgr;1) is provided, whereby carrying out feed to the loop portion by electromagnetic coupling.
摘要:
A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.
摘要:
A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.
摘要翻译:一种乘法处理装置,具有记录电路,用于将基数为(Ypsilon)的M位数(M为自然数)分割成连续的N位数集(N为等于或小于等于 并且用于根据Zgi = Ci *(Ypsilon)N + Si计算中间和Si和中间进位Ci(Z ij是第i集的值(i表示等于或大于预定数的自然数)) 并且用于将与第i组相对应的中间和Si与对应于i的每个值的第(i-1)组相对应的中间进位Ci-1和用于选择具有相同格式的一个或多个数中的一个的选择电路 作为对应于第i组的中间进位Ci的输入,并将所选择的数字输出到编码电路作为与第(i-1)组对应的中间进位Ci-1。
摘要:
Disclosed is a process for preparing a polyarylene sulfide, which involves polycondensing a dihalogenated aromatic compound with a source of sulfur in an organic polar solvent while dehydrating at pressure under which polycondensation is performed. This process avoids dehydration operation of the raw materials, particularly the source of sulfur, prior to polycondensation, thereby resulting in the production of the polyarylene sulfide having a high molecular weight.