公开(公告)号：US20230020359A1

公开(公告)日：2023-01-19

申请号：US17954419

申请日：2022-09-28

申请人： Nitish Paliwal ,  Binal Nasit ,  Peeyush Purohit ,  Kirk S. Yap ,  Raghunandan Makaram ,  Robert G. Blankenship

发明人： Nitish Paliwal ,  Binal Nasit ,  Peeyush Purohit ,  Kirk S. Yap ,  Raghunandan Makaram ,  Robert G. Blankenship

IPC分类号： G06F21/60 ,  G06F21/62 ,  G06F21/85

摘要： In one embodiment, an apparatus includes: a control circuit to receive a message authentication code (MAC) for an epoch comprising a plurality of flits; a calculation circuit to calculate a computed MAC for the epoch; a cryptographic circuit to receive the epoch via a link and decrypt the plurality of flits, prior to authentication of the epoch; and at least one memory to store messages of the decrypted plurality of flits, prior to the authentication of the epoch. Other embodiments are described and claimed.

公开(公告)号：US20100027781A1

公开(公告)日：2010-02-04

申请号：US11961845

申请日：2007-12-20

申请人： Duane E. Galbi ,  David G. Lewis ,  Kirk S. Yap

发明人： Duane E. Galbi ,  David G. Lewis ,  Kirk S. Yap

IPC分类号： H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/24

摘要： A method and apparatus for increasing performance of Data Encryption Standard (DES) and Triple DES (3DES) cipher operation is provided. A critical path through a plurality of rounds in a multi-round cycle to perform a cipher operation is reduced by reducing the number of exclusive OR (XOR) operations in the critical path. An R state element is expanded to 48-bits and each round stage uses the 48-bit expanded R state element which results in a reduction of the number of XOR operations to one per round in the cipher operation plus one additional XOR operation per cipher operation. In addition logic organization is symmetric which further increases the overall performance of DES and 3DES.

摘要翻译： 提供了一种提高数据加密标准（DES）和三重DES（3DES）密码操作性能的方法和装置。 通过减少关键路径中的异或（XOR）异或来减少多轮循环中执行密码操作的多个轮次的关键路径。 R状态元素扩展为48位，每个阶段使用48位扩展的R状态元素，这导致了XOR操作数减少到密码操作中的每一次，加密操作加上一个额外的XOR操作 。 另外逻辑组织是对称的，进一步提高了DES和3DES的整体性能。