公开(公告)号：US20210112132A1

公开(公告)日：2021-04-15

申请号：US17128648

申请日：2020-12-21

申请人： NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

发明人： NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

IPC分类号： H04L29/08 ,  H04L12/741 ,  H04L12/863

摘要： In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

公开(公告)号：US20230020359A1

公开(公告)日：2023-01-19

申请号：US17954419

申请日：2022-09-28

申请人： Nitish Paliwal ,  Binal Nasit ,  Peeyush Purohit ,  Kirk S. Yap ,  Raghunandan Makaram ,  Robert G. Blankenship

发明人： Nitish Paliwal ,  Binal Nasit ,  Peeyush Purohit ,  Kirk S. Yap ,  Raghunandan Makaram ,  Robert G. Blankenship

IPC分类号： G06F21/60 ,  G06F21/62 ,  G06F21/85

摘要： In one embodiment, an apparatus includes: a control circuit to receive a message authentication code (MAC) for an epoch comprising a plurality of flits; a calculation circuit to calculate a computed MAC for the epoch; a cryptographic circuit to receive the epoch via a link and decrypt the plurality of flits, prior to authentication of the epoch; and at least one memory to store messages of the decrypted plurality of flits, prior to the authentication of the epoch. Other embodiments are described and claimed.