摘要:
Disclosed is a packet communication apparatus of large capacity capable of realizing high throughput and packet priority control in packet switching for changing connection of input and output ports of a switch on a variable-length packet unit basis. A variable-length packet is divided into a group of cells in an ingress interface, and the cells are stored in VOQs divided in correspondence with destination output ports of a switch. For each of the VOQs, a corresponding first-cell storing register is provided. When a packet arrives at the head of the VOQ, the first cell indicating an output path of the packet is transferred to a first-cell storing register. Each ingress interface selects one of first cells of packets which can be output and transmits the selected one to the switch. The switch performs a scheduling process so as to select one first cell per output port. The ingress interface to which output permission is given by the scheduling process is connected to a desired output port, and continuously outputs the first cell and the subsequent cells stored in the VOQs to the output port on a packet unit basis.
摘要:
To suppress a server processing load and a network load in a sensor network which accommodates a great number of mobile sensor nodes. Among a plurality of distributed data processing servers (DDS) for managing data of sensor nodes, a distributed data processing server (DDS) that is a home server to hold data of a mobile sensor node is set for each sensor node by a directory server (DRS). At each distributed data processing server (DDS), upon reception of the data from the sensor node, identification process is executed as to whether the data is sensor data to be managed by itself or another distributed data processing server. If a result of the identification is the sensor data to be managed by another distributed data processing server, the data is transferred to the distributed data processing server (DDS-1), which corresponds to the home server of the sensor data, based on setting of the directory server (DRS).
摘要:
A traffic shaper comprises a bandwidth controller 40 having a plurality of leaky bucket units 41-1 to 41-n prepared in correspondence with buffer memories 20-1 to 20-n, and an output queue designation unit 43 for specifying a buffer memory from which a packet is to be read out. Each of the leaky bucket units 41 has a level counter 416 for decrementing the count value at a predetermined rate, and a level increaser 411 to 417 for increasing the count value of the level counter by a value proportional to the product of the length of a transmitted packet and a unitary increment value which is variable depend on the current count value of the level counter.
摘要:
Provided is a high-throughput large-capacity ATM switch in which variation in memory access time and data output delay time generated in the case where a DRAM is used as a cell buffer of the ATM switch is absorbed. To realize this, the ATM switch comprises a first memory using a DRAM for storing cells, a second memory using an SRAM for switching and temporarily storing the cells before transferring the cells to the first memory, and a controller for generating write/read address and timing signals for the first and second memories. The controller generates read address and timing signals for the second memory and write address and timing signals for the first memory taking variation in access time or delay time based on access address of the first memory into account, so that the cells are output on destination output lines after the cells are switched and stored in the second memory and then stored in the first memory.