公开(公告)号：US06256311B1

公开(公告)日：2001-07-03

申请号：US09031775

申请日：1998-02-27

申请人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

发明人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

IPC分类号： H04J314

摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

公开(公告)号：US06252877B1

公开(公告)日：2001-06-26

申请号：US09094678

申请日：1998-06-15

申请人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

发明人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

IPC分类号： H04L1228

CPC分类号： H04L12/5601 ,  H04L49/103 ,  H04L49/108 ,  H04L49/255 ,  H04L49/3009 ,  H04L49/3027 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/505 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5648 ,  H04L2012/5658 ,  H04L2012/5681

摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

摘要翻译： 一种ATM交换系统，包括对应于输出队列的PVC分配电路。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与存储的标识信息相同的PVC识别信息的随后到达的小区被输入到输出缓冲器，并且剩余突发数据的单元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。

公开(公告)号：US5710770A

公开(公告)日：1998-01-20

申请号：US462532

申请日：1995-06-05

申请人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

发明人： Takahiko Kozaki ,  Junichirou Yanagi ,  Kiyoshi Aiki ,  Yutaka Ito ,  Kaoru Aoki ,  Shinobu Gohara

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

公开(公告)号：US5500851A

公开(公告)日：1996-03-19

申请号：US297566

申请日：1994-09-01

申请人： Takahiko Kozaki ,  Nobuhiro Horie ,  Kenichi Asano

发明人： Takahiko Kozaki ,  Nobuhiro Horie ,  Kenichi Asano

IPC分类号： H04Q3/00 ,  H04L12/70 ,  H04L12/931 ,  H04Q3/52 ,  H04Q11/04 ,  H04J1/16 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/106 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5681

摘要： An ATM exchanger includes a plurality of switch units connected in multiple stages, in which a circuit is provided for writing a test cell pattern into and reading it from a buffer memory of each switch unit in accordance with an instruction from a controller, so that the test cell read from the buffer memory can be transferred appropriately to the controller.

摘要翻译： ATM交换机包括多个以多级连接的开关单元，其中提供电路，用于根据来自控制器的指令从每个开关单元的缓冲存储器写入测试单元图形并将其读取， 从缓冲存储器读取的测试单元可以适当地传送到控制器。

公开(公告)号：US5410540A

公开(公告)日：1995-04-25

申请号：US132999

申请日：1993-10-07

申请人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

发明人： Kiyoshi Aiki ,  Takahiko Kozaki ,  Noboru Endo ,  Haruo Shibata

IPC分类号： H04Q3/52 ,  H04L12/18 ,  H04L12/931 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/309 ,  H04L2012/5672

摘要： In a shared-buffer-type ATM switch including a multiplexer, a shared buffer memory, a demultiplexer, a buffer memory controller, a cell copy section is disposed between the multiplexer and the memory. The copy section produces a plurality of copies of a broadcast cell according to information of a copy information table and adds associate routing information to each copied cell so as to write the cells in the memory. In response to an indication from an output counter, the cells are read from the memory to be distributed to output ports, thereby implementing a broadcast function.

摘要翻译： 在包括多路复用器，共享缓冲存储器，解复用器，缓冲存储器控制器的共享缓冲器型ATM交换机中，单元复制部分设置在多路复用器和存储器之间。 复制部分根据复制信息表的信息产生广播小区的多个副本，并将关联路由信息添加到每个复制的小区，以便将单元写入存储器。 响应于来自输出计数器的指示，从存储器读取单元以分配到输出端口，从而实现广播功能。

公开(公告)号：US5214640A

公开(公告)日：1993-05-25

申请号：US570116

申请日：1990-08-17

申请人： Yoshito Sakurai ,  Takahiko Kozaki ,  Shirou Tanabe

发明人： Yoshito Sakurai ,  Takahiko Kozaki ,  Shirou Tanabe

IPC分类号： H04Q3/00 ,  H04L12/931

CPC分类号： H04L49/3009 ,  H04L49/103 ,  H04L49/25 ,  H04L49/45

摘要： A switching system which comprises an initial stage including the plurality of first switch devices and in which respective input terminals of the plurality of first switch devices are connected in common to corresponding one incoming highway, and each first switch device selectively delivers to its output terminal an inputted packet in accordance with routing information of the packet so that packets of different outgoing highway numbers are delivered out of the output terminals of the respective first switch devices, and a final stage including the plurality of second switch devices and in which each output terminal of the respective second switch devices is connected to corresponding one outgoing highway, and respective input terminals of a particular second switch device are connected to respective output terminals of the first switch devices which deliver outgoing highways of the same numbers as those of outgoing highways connected to the particular second switch device.

摘要翻译： 一种交换系统，包括包括多个第一开关装置的初始阶段，并且多个第一开关装置的各个输入端子共同连接到相应的一个输入高速公路，并且每个第一开关装置选择性地将其输出到其输出端子 根据分组的路由信息​​输入分组，使得不同的出局公路号码的分组从各个第一交换设备的输出端传送出去，最后一级包括多个第二交换设备，其中每个输出终端的 相应的第二开关装置连接到对应的一个输出高速公路，并且特定的第二开关装置的各个输入端子连接到第一开关装置的相应输出端子，该第一开关装置输出与输出高速公路连接的输出高速公路相同数量的输出高速公路 特定的第二开关装置。

公开(公告)号：US5144622A

公开(公告)日：1992-09-01

申请号：US593762

申请日：1990-10-05

申请人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Michio Asano ,  Masashi Ohno ,  Takahiko Kozaki

发明人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Michio Asano ,  Masashi Ohno ,  Takahiko Kozaki

IPC分类号： H04L12/46 ,  H04L12/56

CPC分类号： H04L45/742 ,  H04L12/4604 ,  H04L45/34

摘要： In a network system having a plurality of LANs each connecting a plurality of terminals interconnected, a LAN interconnection switching unit for switching and relaying data receives data frames from LANs and sends out a call set-up frame including a call number assigned to a combination of source and destination terminal addresses and addresses of relaying interconnection switching units. The data received from LAN is segmented into packets, which are sent out together with the call number. The interconnection switching unit switches and relays data by using data frame error detection scheme in the LAN. Information for controlling a switching sequence is added to the data frame from the LAN to prevent the interruption by the packet having a different call number.

摘要翻译： 在具有互连的多个LAN的多个LAN的网络系统中，用于切换和中继数据的LAN互连切换单元从LAN接收数据帧，并发出包括分配给组合的呼叫号码的呼叫建立帧 中继互连交换单元的源和目的终端地址和地址。 从LAN接收的数据被分割成与呼叫号码一起发送的分组。 互连交换单元通过使用LAN中的数据帧错误检测方案来切换和中继数据。 用于控制切换序列的信息从LAN被添加到数据帧，以防止具有不同呼叫号码的分组的中断。

公开(公告)号：US5099475A

公开(公告)日：1992-03-24

申请号：US564617

申请日：1990-08-09

申请人： Takahiko Kozaki ,  Noboru Endo ,  Yoshito Sakurai

发明人： Takahiko Kozaki ,  Noboru Endo ,  Yoshito Sakurai

IPC分类号： H04Q3/52 ,  H04L12/931 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L49/108 ,  H04L2012/5672

摘要： A switching system for switching communication information between "M" incoming highways and "N" outgoing highways by using fixed-length cells, each having a header section and a data section and according to information contained in the header section (where "M" and "N" are integers), comprising: a demultiplexing unit for demultiplexing each incoming highway into a plurality of first output links; a switch unit, having the first output links of the demultiplexing unit as first input links and a plurality of second output links, for switching communication information between the first input links and the second output links; and a multiplexing unit, having "N" groups of input links, each group being formed by grouping a specified number of second output links, for multiplexing the cells on the second output links of each group and outputting them through one of third output links to a corresponding outgoing highway.

摘要翻译： 一种用于通过使用固定长度小区在“M”条进入高速公路和“N”条出站高速公路之间切换通信信息的交换系统，每个具有报头部分和数据部分，并根据包含在报头部分中的信息（其中“M”和 “N”是整数），包括：解复用单元，用于将每个进入的公路解复用为多个第一输出链路; 开关单元，具有多路复用单元的第一输出链路作为第一输入链路和多个第二输出链路，用于切换第一输入链路和第二输出链路之间的通信信息; 以及具有“N”组输入链路的复用单元，每组通过对指定数量的第二输出链路进行分组而形成，用于对每组的第二输出链路上的单元进行多路复用，并将它们通过第三输出链路之一输出到 相应的出行公路。

公开(公告)号：US06977941B2

公开(公告)日：2005-12-20

申请号：US09791791

申请日：2001-02-26

申请人： Masami Takahashi ,  Akio Makimoto ,  Takahiko Kozaki ,  Takayuki Kanno ,  Yasuo Oginuma ,  Kaori Nakayama ,  Mitsuhiro Wada ,  Norihiko Moriwaki ,  Masumi Fukano ,  Yusho Futami

发明人： Masami Takahashi ,  Akio Makimoto ,  Takahiko Kozaki ,  Takayuki Kanno ,  Yasuo Oginuma ,  Kaori Nakayama ,  Mitsuhiro Wada ,  Norihiko Moriwaki ,  Masumi Fukano ,  Yusho Futami

IPC分类号： H04L12/56 ,  G06F12/00

CPC分类号： H04L49/103 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/40

摘要： A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.

摘要翻译： 一种分组交换机，具有以固定长度数据块单位为基础将从每个输入线路接收的可变长度分组写入共享缓冲存储器的结构，其中缓冲器控制器为每个输入线路形成输入队列，并且当最后数据 可变长度分组的块被登记在输入队列中，将用于输入队列的链接地址列表链接到对应于一个或多个分组目的地输出线的一个或多个输出队列。

公开(公告)号：US06389026B1

公开(公告)日：2002-05-14

申请号：US09031775

申请日：1998-02-27

申请人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

发明人： Takahiko Kozaki ,  Morihito Miyagi ,  Manabu Okamoto

IPC分类号： H04J314

CPC分类号： H04L12/5601 ,  H04L49/103 ,  H04L49/108 ,  H04L49/255 ,  H04L49/3009 ,  H04L49/3027 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/505 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5648 ,  H04L2012/5658 ,  H04L2012/5681

摘要： An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells, having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.

摘要翻译： 一种ATM交换系统，包括对应于输出队列的PVC分配电路。 在每个突发数据的前导单元到达时，如果输出线有空间，则突发数据的PVC被存储为用于准入和识别的信息。 具有与所存储的标识信息相同的PVC识别信息的随后到达的信元被输入到输出缓冲器，并且剩余突发数据的信元全部被丢弃。 即使当多个突发数据竞争相同的输出线时，除了首次到达的入站突发数据之外的所有小区被丢弃的事实也防止了小区在预定带宽之外的输入，并且定位了受到 由于输出队列溢出而导致的单元丢弃。