公开(公告)号：US11665710B2

公开(公告)日：2023-05-30

申请号：US17190349

申请日：2021-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04W72/04 ,  H04W88/08

CPC classification number: H04W72/0433 ,  H04W88/085 ,  Y02D30/70

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system allocates the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11658687B2

公开(公告)日：2023-05-23

申请号：US17394597

申请日：2021-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeremy Chritz ,  Tamara Schmitz ,  Fa-Long Luo ,  Jaime Cummins

IPC: H04L27/04 ,  H04L27/12 ,  H04L27/20 ,  H04B1/00 ,  H04L27/26

CPC classification number: H04B1/0039 ,  H04L27/2601

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to the wireless protocol in the RF wireless domain. A computing device may be trained to generate coefficient data based on the operations of a wireless transceiver such that mixing input data using the coefficient data generates an approximation of the output data, as if it were processed by the wireless transceiver. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11573903B2

公开(公告)日：2023-02-07

申请号：US16864437

申请日：2020-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: G06F12/10 ,  G06F12/02

Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.

公开(公告)号：US11539502B2

公开(公告)日：2022-12-27

申请号：US17090123

申请日：2020-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: H04L7/04 ,  H04L27/00 ,  H04L27/26

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (RF) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. The electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. A decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. Examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US11422929B2

公开(公告)日：2022-08-23

申请号：US17150675

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: G06F12/02 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/06

Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

公开(公告)号：US20210319823A1

公开(公告)日：2021-10-14

申请号：US16844997

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F9/30 ,  G06F9/50 ,  G06F9/38 ,  G06N3/063 ,  H04N5/232

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US20210319821A1

公开(公告)日：2021-10-14

申请号：US16844988

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F12/0813 ,  G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06N3/063

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; and an interface to a memory controller. The interface may be configured to facilitate access to the random access memory by the memory controller. In response to an indication provided in the random access memory, the Deep Learning Accelerator may execute the instructions to apply input that is stored in the random access memory to the Artificial Neural Network, generate output from the Artificial Neural Network, and store the output in the random access memory.

公开(公告)号：US11070257B2

公开(公告)日：2021-07-20

申请号：US16786637

申请日：2020-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04B7/0413 ,  G06N3/08 ,  G06N3/04

Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.

公开(公告)号：US11032139B2

公开(公告)日：2021-06-08

申请号：US16116849

申请日：2018-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

IPC: H04L12/24 ,  H04L29/08 ,  H04W76/28

Abstract: Examples described herein include methods, devices, and systems which may implement different processing stages for wireless communication in processing units. Such data processing may include a source data processing stage, a baseband processing stage, a digital front-end processing stage, and a radio frequency (RF) processing stage. Data may be received from a sensor of device and then processed in the stages to generate output data for transmission. Processing the data in the various stages may occur during an active time period of a discontinuous operating mode. During the active time period, a reconfigurable hardware platform may allocate all or a portion of the processing units to implement the processing stages. Examples of systems and methods described herein may facilitate the processing of data for 5G (e.g., New Radio (NR)) wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US10963265B2

公开(公告)日：2021-03-30

申请号：US15493551

申请日：2017-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

IPC: G06F9/38 ,  G06F15/78

Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).