公开(公告)号：US09892777B2

公开(公告)日：2018-02-13

申请号：US15676608

申请日：2017-08-14

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2297

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

公开(公告)号：US09858979B1

公开(公告)日：2018-01-02

申请号：US15286259

申请日：2016-10-05

Applicant: Micron Technology, Inc.

Inventor： Scott James Derner ,  Christopher John Kawamura ,  Charles L. Ingalls

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.

公开(公告)号：US20170270990A1

公开(公告)日：2017-09-21

申请号：US15071490

申请日：2016-03-16

Applicant: Micron Technology, Inc.

Inventor： Christopher John Kawamura ,  Scott James Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.