公开(公告)号：US20180330791A1

公开(公告)日：2018-11-15

申请号：US15976315

申请日：2018-05-10

申请人： The Penn State Research Foundation

发明人： Xueqing Li ,  Sumitha George ,  John Sampson ,  Sumeet Gupta ,  Suman Datta ,  Vijaykrishnan Narayanan ,  Kaisheng Ma

IPC分类号： G11C14/00 ,  H01L29/78 ,  G11C13/00

CPC分类号： G11C14/0072 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/223 ,  G11C11/2275 ,  G11C11/2293 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H01L29/78391

摘要： Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the IDS−VG hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two IDS states at VG=0.

公开(公告)号：US09966128B1

公开(公告)日：2018-05-08

申请号：US15463394

申请日：2017-03-20

申请人： GLOBALFOUNDRIES Inc.

发明人： Germain Bossu

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C5/06 ,  G11C5/14

CPC分类号： G11C11/2275 ,  G11C5/063 ,  G11C5/148 ,  G11C7/20 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/412 ,  G11C14/0072

摘要： The present disclosure provides a storage cell or storage structure having a static RAM-like operational behavior while nevertheless providing non-volatile storage capability on a single bit basis. To this end, a non-volatile storage element, such as a ferroelectric transistor element, may be provided within an inverter structure so as to allow the storage of a logic state at any desired operational phase by increasing the voltage difference used for operating the inverter structure. In illustrative embodiments, the stored logic state may be re-established during a power-up event.

公开(公告)号：US09966127B2

公开(公告)日：2018-05-08

申请号：US15291711

申请日：2016-10-12

申请人： Micron Technology, Inc.

发明人： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC分类号： G11C11/22

CPC分类号： G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

摘要： Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

公开(公告)号：US20170366938A1

公开(公告)日：2017-12-21

申请号：US15674328

申请日：2017-08-10

申请人： Ivani, LLC

发明人： John Wootton ,  Matthew Wootton ,  Chris Nissman ,  Victoria Preston ,  Jonathan Clark ,  Justin McKinney ,  Claire Barnes ,  Xinyu Xiao ,  Zhecan Wang

IPC分类号： H04W4/02 ,  H04W4/04 ,  H04L5/00 ,  H04B17/318 ,  H04L1/00 ,  G01V3/12 ,  H04W64/00 ,  H04W4/00

CPC分类号： H04W4/023 ,  G01V1/001 ,  G01V3/12 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  H04B17/27 ,  H04B17/318 ,  H04L1/0018 ,  H04L5/006 ,  H04W4/30 ,  H04W4/33 ,  H04W4/80 ,  H04W64/00

摘要： Systems and methods for detecting the presence of a body in a network without fiducial elements, using signal absorption, and signal forward and reflected backscatter of radio frequency (RF) waves caused by the presence of a biological mass in a communications network.

公开(公告)号：US20170365322A1

公开(公告)日：2017-12-21

申请号：US15692994

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Christopher John Kawamura ,  Scott James Derner

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C7/14 ,  G11C11/221 ,  G11C11/2293

摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

公开(公告)号：US20170352396A1

公开(公告)日：2017-12-07

申请号：US15659994

申请日：2017-07-26

申请人： Micron Technology, Inc.

发明人： Eric S. Carman

IPC分类号： G11C11/22 ,  G11C11/56 ,  G11C8/08 ,  G11C13/04

CPC分类号： G11C11/225 ,  G11C8/08 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C13/047

摘要： Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

公开(公告)号：US20170256300A1

公开(公告)日：2017-09-07

申请号：US15057914

申请日：2016-03-01

申请人： Micron Technology, Inc.

发明人： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2293

摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US09697913B1

公开(公告)日：2017-07-04

申请号：US15179695

申请日：2016-06-10

申请人： Micron Technology, Inc.

发明人： Marcello Mariani ,  Giorgio Servalli ,  Andrea Locatelli

IPC分类号： G11C11/22 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C11/2253 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297

摘要： Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

公开(公告)号：US08787063B2

公开(公告)日：2014-07-22

申请号：US13559531

申请日：2012-07-26

申请人： Joseph T. Evans, Jr. ,  Calvin B. Ward

发明人： Joseph T. Evans, Jr. ,  Calvin B. Ward

IPC分类号： G11C11/22

CPC分类号： G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

摘要翻译： 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使由具有至少三个状态的数据值确定的值存储在当前连接到写入线的铁电存储单元中。 读取电路测量存储在当前连接到读取线的铁电存储器单元中的电荷。

公开(公告)号：US20120134196A1

公开(公告)日：2012-05-31

申请号：US12956845

申请日：2010-11-30

申请人： Joseph T. Evans, JR. ,  Calvin B. Ward

发明人： Joseph T. Evans, JR. ,  Calvin B. Ward

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

摘要翻译： 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。